View LVCMOS12-F12_8604686.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

ds181 (v1.21) september 27, 2016 www.xilinx.com product specification 1 ? 2011? 2016 xilinx, inc. xilinx, the xilinx logo, artix, virtex, kintex, zynq, spartan, ise, vivado and other designated brand s included herein are trademarks of xilinx in the united states and other countries. all other tradema rks are the property of their respective owners. introduction artix?-7 fpgas are available in -3, -2, -1, -1li, and -2l speed grades, with -3 having the highest performance. the artix-7 fpgas predominantly oper ate at a 1.0v core voltage. the -1li and -2l devices are screened for lower maximum static power and can operate at lower core voltages for lower dynamic power than the -1 and -2 devices, respectively. the -1li de vices operate only at v ccint =v ccbram = 0.95v and have the same speed specifications as the -1 speed grade. the -2l devices can operate at either of two v ccint voltages, 0.9v and 1.0v and are screened for lower maxi mum static power. when operated at v ccint = 1.0v, the speed specification of a -2l device is the same as the -2 speed grade. when operated at v ccint = 0.9v, the -2l static and dynamic power is reduced. artix-7 fpga dc and ac characteristics are specified in commercial, extended, industrial, expanded (-1q), and military (-1m) temperature ra nges. except the operating temperature range or unless otherwise noted, all the dc and ac electrical parameters are the same for a particular speed grade (that is, the timing characteristics of a -1m speed grade military device are the same as for a -1c speed grade commercial device). however, only selected speed grades and/or devices are available in each temperature range. for example, -1m is only available in the defense-grade artix-7q family and -1q is only available in xa artix-7 fpgas. all supply voltage and junction temperature specifications are representative of worst-ca se conditions. the parameters included are common to popular designs and typical applications. available device and package combinations can be found in : ? 7 series fpgas overview ( ds180 ) ? defense-grade 7 series fpgas overview ( ds185 ) ? xa artix-7 fpgas overview ( ds197 ) this artix-7 fpga data sheet, part of an overall set of documentation on the 7 series fpgas, is available on the xilinx website at www.xilinx.com/ documentation . dc characteristics artix-7 fpgas data sheet: dc and ac switching characteristics ds181 (v1.21) september 27, 2016 product specification table 1: absolute maximum ratings (1) symbol description min max units fpga logic v ccint internal supply voltage ?0.5 1.1 v v ccaux auxiliary supply voltage ?0.5 2.0 v v ccbram supply voltage for the block ram memories ?0.5 1.1 v v cco output drivers supply voltage for hr i/o banks ?0.5 3.6 v v ref input reference voltage ?0.5 2.0 v v in (2)(3)(4) i/o input voltage ?0.4 v cco +0.55 v i/o input voltage (when v cco = 3.3v) for v ref and differential i/o standards except tmds_33 (5) ?0.4 2.625 v v ccbatt key memory battery backup supply ?0.5 2.0 v gtp transceiver v mgtavcc analog supply voltage for the gtp tran smitter and receiver circuits ?0.5 1.1 v v mgtavtt analog supply voltage for the gtp transmitter and receiver termination circuits ?0.5 1.32 v v mgtrefclk reference clock absolute input voltage ?0.5 1.32 v v in receiver (rxp/rxn) and transmitter (txp /txn) absolute input voltage ?0.5 1.26 v s e n d f e e d b a c k
artix-7 fpgas data sheet: dc and ac switching characteristics ds181 (v1.21) september 27, 2016 www.xilinx.com product specification 2 i dcin-float dc input current for receiver input pins dc coupled rx termination = floating ? 14 ma i dcin-mgtavtt dc input current for receiver input pins dc coupled rx termination = v mgtavtt ? 12 ma i dcin-gnd dc input current for receiver input pins dc coupled rx termination = gnd ? 6.5 ma i dcout-float dc output current for transmitter pins dc coupled rx termination = floating ? 14 ma i dcout-mgtavtt dc output current for transmitter pins dc coupled rx termination = v mgtavtt ? 12 ma xadc v ccadc xadc supply relative to gndadc ?0.5 2.0 v v refp xadc reference input relative to gndadc ?0.5 2.0 v temperature t stg storage temperature (ambient) ?65 150 c t sol maximum soldering temperature for pb/sn component bodies (6) ?+220c maximum soldering temperature for pb-free component bodies (6) ?+260c t j maximum junction temperature (6) ?+125c notes: 1. stresses beyond those listed under absolute maximum ratings might cause permanent damage to the device. these are stress rati ngs only, and functional operation of the device at these or any other c onditions beyond those listed under operating conditions is not i mplied. exposure to absolute maximum ratings conditions for extended periods of time might affect device reliability. 2. the lower absolute voltage specification always applies. 3. for i/o operation, refer to 7 series fpgas selectio resources user guide ( ug471 ). 4. the maximum limit applies to dc signals. for maximum undershoot and overshoot ac specifications, see table 4 . 5. see table 9 for tmds_33 specifications. 6. for soldering guidelines and thermal considerations, see 7 series fpga packaging and pinout specification ( ug475 ). table 2: recommended operating conditions (1)(2) symbol description min typ max units fpga logic v ccint (3) for -3, -2, -2le (1.0v), -1, -1q, -1m dev ices: internal supply voltage 0.95 1.00 1.05 v for -1li (0.95v) devices: internal supply voltage 0.92 0.95 0.98 v for -2le (0.9v) devices: internal supply voltage 0.87 0.90 0.93 v v ccaux auxiliary supply voltage 1.71 1.80 1.89 v v ccbram (3) for -3, -2, -2le (1.0v), -2le (0.9v), -1, -1q, -1m devices: block ram supply voltage 0.95 1.00 1.05 v for -1li (0.95v) devices: block ram supply voltage 0.92 0.95 0.98 v v cco (4)(5) supply voltage for hr i/o banks 1.14 ? 3.465 v v in (6) i/o input voltage ?0.20 ? v cco +0.20 v i/o input voltage (when v cco = 3.3v) for v ref and differential i/o standards except tmds_33 (7) ?0.20 ? 2.625 v i in (8) maximum current through any pin in a powered or unpowered bank when forward biasing the clamp diode. ?? 10ma v ccbatt (9) battery voltage 1.0 ? 1.89 v gtp transceiver v mgtavcc (10) analog supply voltage for the gtp transmitt er and receiver circuits 0.97 1.0 1.03 v v mgtavtt (10) analog supply voltage for the gtp transmitter and receiver termination circuits 1.17 1.2 1.23 v xadc v ccadc xadc supply relative to gndadc 1.71 1.80 1.89 v table 1: absolute maximum ratings (1) (cont?d) symbol description min max units s e n d f e e d b a c k
artix-7 fpgas data sheet: dc and ac switching characteristics ds181 (v1.21) september 27, 2016 www.xilinx.com product specification 3 v refp externally supplied reference voltage 1.20 1.25 1.30 v temperature t j junction temperature operating range for commercial (c) temperature devices 0 ? 85 c junction temperature operating range for extended (e) temperature devices 0 ? 100 c junction temperature operating range for in dustrial (i) temperature devices ?40 ? 100 c junction temperature operating range for expanded (q) temperature devices ?40 ? 125 c junction temperature operating range for m ilitary (m) temperature devices ?55 ? 125 c notes: 1. all voltages are relative to ground. 2. for the design of the power distribution system consult 7 series fpgas pcb design and pin planning guide ( ug483 ). 3. if v ccint and v ccbram are operating at the same voltage, v ccint and v ccbram should be connected to the same supply. 4. configuration data is retained even if v cco drops to 0v. 5. includes v cco of 1.2v, 1.5v, 1.8v, 2.5v, and 3.3v at 5%. 6. the lower absolute voltage specification always applies. 7. see table 9 for tmds_33 specifications. 8. a total of 200 ma per bank should not be exceeded. 9. v ccbatt is required only when using bitstream encryp tion. if battery is not used, connect v ccbatt to either ground or v ccaux . 10. each voltage listed requires the filter circuit described in 7 series fpgas gtp transceiver user guide ( ug482 ). table 3: dc characteristics over re commended operating conditions symbol description min typ (1) max units v drint data retention v ccint voltage (below which configuration data might be lost) 0.75 ? ? v v dri data retention v ccaux voltage (below which configur ation data might be lost) 1.5 ? ? v i ref v ref leakage current per pin ? ? 15 a i l input or output leakage current per pin (sample-tested) ? ? 15 a c in (2) die input capacitance at the pad ? ? 8 pf i rpu pad pull-up (when selected) @ v in =0v, v cco =3.3v 90 ? 330 a pad pull-up (when selected) @ v in =0v, v cco =2.5v 68 ? 250 a pad pull-up (when selected) @ v in =0v, v cco =1.8v 34 ? 220 a pad pull-up (when selected) @ v in =0v, v cco =1.5v 23 ? 150 a pad pull-up (when selected) @ v in =0v, v cco =1.2v 12 ? 120 a i rpd pad pull-down (when selected) @ v in =3.3v 68 ? 330 a i ccadc analog supply current, analog circ uits in powered up state ? ? 25 ma i batt (3) battery supply current ? ? 150 na r in_term (4) thevenin equivalent resistance of programmable input termination to v cco /2 (untuned_split_40) 28 40 55 thevenin equivalent resistance of programmable input termination to v cco /2 (untuned_split_50) 35 50 65 thevenin equivalent resistance of programmable input termination to v cco /2 (untuned_split_60) 44 60 83 table 2: recommended operating conditions (1)(2) (cont?d) symbol description min typ max units s e n d f e e d b a c k
artix-7 fpgas data sheet: dc and ac switching characteristics ds181 (v1.21) september 27, 2016 www.xilinx.com product specification 4 n temperature diode ideality factor ? 1.010 ? ? r temperature diode series resistance ? 2 ? notes: 1. typical values are specified at nominal voltage, 25c. 2. this measurement represents the die capacitance at the pad, not including the package. 3. maximum value specified for worst case process at 25c. 4. termination resistance to a v cco /2 level. table 4: v in maximum allowed ac voltage overshoot and undershoot for hr i/o banks (1)(2) ac voltage overshoot % of ui @?55c to 125c ac voltage undershoot % of ui @?55c to 125c v cco + 0.55 100 ?0.40 100 ?0.45 61.7 ?0.50 25.8 ?0.55 11.0 v cco + 0.60 46.6 ?0.60 4.77 v cco + 0.65 21.2 ?0.65 2.10 v cco + 0.70 9.75 ?0.70 0.94 v cco + 0.75 4.55 ?0.75 0.43 v cco + 0.80 2.15 ?0.80 0.20 v cco + 0.85 1.02 ?0.85 0.09 v cco + 0.90 0.49 ?0.90 0.04 v cco + 0.95 0.24 ?0.95 0.02 notes: 1. a total of 200 ma per bank should not be exceeded. 2. the peak voltage of the overshoot or undershoot, and the duration above v cco + 0.20v or below gnd ? 0.20v, must not exceed the values in this table. table 3: dc characteristics over re commended operating conditions (cont?d) symbol description min typ (1) max units s e n d f e e d b a c k
artix-7 fpgas data sheet: dc and ac switching characteristics ds181 (v1.21) september 27, 2016 www.xilinx.com product specification 5 table 5: typical quiescent supply current symbol description device speed grade units 1.0v 0.95v 0.9v -3 -2 -2le -1 -1li -2le i ccintq quiescent v ccint supply current xc7a12t 48 48 48 48 43 38 ma xc7a15t 95 95 95 95 58 66 ma xc7a25t 48 48 48 48 43 38 ma xc7a35t 95 95 95 95 58 66 ma xc7a50t 95 95 95 95 58 66 ma xc7a75t 155 155 155 155 96 108 ma xc7a100t 155 155 155 155 96 108 ma xc7a200t 328 328 328 328 203 232 ma xa7a15t n/a 95 n/a 95 n/a n/a ma xa7a35t n/a 95 n/a 95 n/a n/a ma xa7a50t n/a 95 n/a 95 n/a n/a ma xa7a75t n/a 155 n/a 155 n/a n/a ma xa7a100t n/a 155 n/a 155 n/a n/a ma xq7a50t n/a 95 n/a 95 58 n/a ma xq7a100t n/a 155 n/a 155 96 n/a ma xq7a200t n/a 328 n/a 328 203 n/a ma i ccoq quiescent v cco supply current xc7a12t 1 1 1 1 1 1 ma xc7a15t111111ma xc7a25t111111ma xc7a35t111111ma xc7a50t111111ma xc7a75t444444ma xc7a100t 4 4 4 4 4 4 ma xc7a200t 5 5 5 5 5 5 ma xa7a15t n/a 1 n/a 1 n/a n/a ma xa7a35t n/a 1 n/a 1 n/a n/a ma xa7a50t n/a 1 n/a 1 n/a n/a ma xa7a75t n/a 4 n/a 4 n/a n/a ma xa7a100t n/a 4 n/a 4 n/a n/a ma xq7a50t n/a 1 n/a 1 1 n/a ma xq7a100t n/a 4 n/a 4 4 n/a ma xq7a200t n/a 5 n/a 5 5 n/a ma s e n d f e e d b a c k
artix-7 fpgas data sheet: dc and ac switching characteristics ds181 (v1.21) september 27, 2016 www.xilinx.com product specification 6 i ccauxq quiescent v ccaux supply current xc7a12t 13 13 13 13 13 13 ma xc7a15t 22 22 22 22 19 22 ma xc7a25t 13 13 13 13 13 13 ma xc7a35t 22 22 22 22 19 22 ma xc7a50t 22 22 22 22 19 22 ma xc7a75t 36 36 36 36 32 36 ma xc7a100t 36 36 36 36 32 36 ma xc7a200t 73 73 73 73 65 73 ma xa7a15t n/a 22 n/a 22 n/a n/a ma xa7a35t n/a 22 n/a 22 n/a n/a ma xa7a50t n/a 22 n/a 22 n/a n/a ma xa7a75t n/a 36 n/a 36 n/a n/a ma xa7a100t n/a 36 n/a 36 n/a n/a ma xq7a50t n/a 22 n/a 22 19 n/a ma xq7a100t n/a 36 n/a 36 32 n/a ma xq7a200t n/a 73 n/a 73 65 n/a ma i ccbramq quiescent v ccbram supply current xc7a12t 1 1 1 1 1 1 ma xc7a15t222212ma xc7a25t111111ma xc7a35t222212ma xc7a50t222212ma xc7a75t444424ma xc7a100t 4 4 4 4 2 4 ma xc7a200t 11 11 11 11 6 11 ma xa7a15t n/a 2 n/a 2 n/a n/a ma xa7a35t n/a 2 n/a 2 n/a n/a ma xa7a50t n/a 2 n/a 2 n/a n/a ma xa7a75t n/a 4 n/a 4 n/a n/a ma xa7a100t n/a 4 n/a 4 n/a n/a ma xq7a50t n/a 2 n/a 2 1 n/a ma xq7a100t n/a 4 n/a 4 2 n/a ma xq7a200t n/a 11 n/a 11 6 n/a ma notes: 1. typical values are specified at nominal voltage, 85c junction temperature (t j ) with single-ended selectio resources. 2. typical values are for blank configured devices with no output current loads, no active input pull-up resistors, all i/o pins are 3-state and floating. 3. use the xilinx power estimator (xpe) spreadsheet tool (download at http://www.xilinx.com/power ) to estimate static power consumption for conditions other than those specified. table 5: typical quiescent supply current (cont?d) symbol description device speed grade units 1.0v 0.95v 0.9v -3 -2 -2le -1 -1li -2le s e n d f e e d b a c k
artix-7 fpgas data sheet: dc and ac switching characteristics ds181 (v1.21) september 27, 2016 www.xilinx.com product specification 7 power-on/off power supply sequencing the recommended power-on sequence is v ccint , v ccbram , v ccaux , and v cco to achieve minimum current draw and ensure that the i/os are 3-stated at power-on. the recommended power-off se quence is the reverse of the power-on sequence. if v ccint and v ccbram have the same recommended voltage levels then bo th can be powered by the same supply and ramped simultaneously. if v ccaux and v cco have the same recommended voltage levels then both can be powered by the same supply and ramped simultaneously. for v cco voltages of 3.3v in hr i/o banks and configuration bank 0: ? the voltage difference between v cco and v ccaux must not exceed 2.625v for longer than t vcco2vccaux for each power-on/off cycle to maintain device reliability levels. ?the t vcco2vccaux time can be allocated in any percentage between the power-on and power-off ramps. the recommended power-on sequence to achieve minimum current draw for the gtp transceivers is v ccint , v mgtavcc , v mgtavtt or v mgtavcc , v ccint , v mgtavtt . both v mgtavcc and v ccint can be ramped simultaneously. the recommended power-off sequence is the reverse of the power- on sequence to achieve minimum current draw. if these recommended sequences ar e not met, current drawn from v mgtavtt can be higher than specifications during power- up and power-down. ?when v mgtavtt is powered before v mgtavcc and v mgtavtt ?v mgtavcc > 150 mv and v mgtavcc <0.7v, the v mgtavtt current draw can increase by 460 ma per transceiver during v mgtavcc ramp up. the duration of the current draw can be up to 0.3 x t mgtavcc (ramp time from gnd to 90% of v mgtavcc ). the reverse is true for power-down. ?when v mgtavtt is powered before v ccint and v mgtavtt ?v ccint > 150 mv and v ccint <0.7v, the v mgtavtt current draw can increase by 50 ma per transceiver during v ccint ramp up. the duration of th e current draw can be up to 0.3 x t vccint (ramp time from gnd to 90% of v ccint ). the reverse is tr ue for power-down. there is no recommended sequence for supplies not shown. table 6 shows the minimum current, in addition to i ccq , that is required by artix-7 devices for proper power-on and configuration. if the current minimums shown in table 5 and table 6 are met, the device powers on after all four supplies have passed through their power-on re set threshold voltages. the fpga mu st not be configured until after v ccint is applied. once initialized and configured, use the xilinx power estima tor (xpe) tools to estimate current drain on these supplies. table 6: power-on current for artix-7 devices device i ccintmin i ccauxmin i ccomin i ccbrammin units xc7a12t i ccintq +120 i ccauxq +40 i ccoq + 40 ma per bank i ccbramq +60 ma xc7a15t i ccintq +120 i ccauxq +40 i ccoq + 40 ma per bank i ccbramq +60 ma xc7a25t i ccintq +120 i ccauxq +40 i ccoq + 40 ma per bank i ccbramq +60 ma xc7a35t i ccintq +120 i ccauxq +40 i ccoq + 40 ma per bank i ccbramq +60 ma xc7a50t i ccintq +120 i ccauxq +40 i ccoq + 40 ma per bank i ccbramq +60 ma xc7a75t i ccintq +170 i ccauxq +40 i ccoq + 40 ma per bank i ccbramq +60 ma xc7a100t i ccintq +170 i ccauxq +40 i ccoq + 40 ma per bank i ccbramq +60 ma xc7a200t i ccintq +340 i ccauxq +50 i ccoq + 40 ma per bank i ccbramq +80 ma xa7a15t i ccintq +120 i ccauxq +40 i ccoq + 40 ma per bank i ccbramq +60 ma xa7a35t i ccintq +120 i ccauxq +40 i ccoq + 40 ma per bank i ccbramq +60 ma xa7a50t i ccintq +120 i ccauxq +40 i ccoq + 40 ma per bank i ccbramq +60 ma xa7a75t i ccintq +170 i ccauxq +40 i ccoq + 40 ma per bank i ccbramq +60 ma xa7a100t i ccintq +170 i ccauxq +40 i ccoq + 40 ma per bank i ccbramq +60 ma xq7a50t i ccintq +120 i ccauxq +40 i ccoq + 40 ma per bank i ccbramq +60 ma xq7a100t i ccintq +170 i ccauxq +40 i ccoq + 40 ma per bank i ccbramq +60 ma xq7a200t i ccintq +340 i ccauxq +50 i ccoq + 40 ma per bank i ccbramq +80 ma s e n d f e e d b a c k
artix-7 fpgas data sheet: dc and ac switching characteristics ds181 (v1.21) september 27, 2016 www.xilinx.com product specification 8 dc input and output levels values for v il and v ih are recommended input voltages. values for i ol and i oh are guaranteed over the recommended operating conditions at the v ol and v oh test points. only selected standards are te sted. these are chosen to ensure that all standards meet their specific ations. the selected standards are tested at a minimum v cco with the respective v ol and v oh voltage levels shown. other standards are sample tested. table 7: power supply ramp time symbol description conditions min max units t vccint ramp time from gnd to 90% of v ccint 0.2 50 ms t vcco ramp time from gnd to 90% of v cco 0.2 50 ms t vccaux ramp time from gnd to 90% of v ccaux 0.2 50 ms t vccbram ramp time from gnd to 90% of v ccbram 0.2 50 ms t vcco2vccaux allowed time per power cycle for v cco ? v ccaux > 2.625v t j = 125c (1) ?300 ms t j = 100c (1) ?500 t j = 85c (1) ?800 t mgtavcc ramp time from gnd to 90% of v mgtavcc 0.2 50 ms t mgtavtt ramp time from gnd to 90% of v mgtavtt 0.2 50 ms notes: 1. based on 240,000 power cycles with nominal v cco of 3.3v or 36,500 power cycles with worst case v cco of 3.465v. table 8: selectio dc input and output levels (1)(2) i/o standard v il v ih v ol v oh i ol i oh v, min v, max v, min v, max v, max v, min ma, max ma, min hstl_i ?0.300 v ref ? 0.100 v ref + 0.100 v cco + 0.300 0.400 v cco ? 0.400 8.00 ?8.00 hstl_i_18 ?0.300 v ref ? 0.100 v ref + 0.100 v cco + 0.300 0.400 v cco ? 0.400 8.00 ?8.00 hstl_ii ?0.300 v ref ? 0.100 v ref + 0.100 v cco + 0.300 0.400 v cco ? 0.400 16.00 ?16.00 hstl_ii_18 ?0.300 v ref ? 0.100 v ref + 0.100 v cco + 0.300 0.400 v cco ? 0.400 16.00 ?16.00 hsul_12 ?0.300 v ref ? 0.130 v ref + 0.130 v cco + 0.300 20% v cco 80% v cco 0.10 ?0.10 lvcmos12 ?0.300 35% v cco 65% v cco v cco + 0.300 0.400 v cco ?0.400 note 3 note 3 lvcmos15 ?0.300 35% v cco 65% v cco v cco + 0.300 25% v cco 75% v cco note 4 note 4 lvcmos18 ?0.300 35% v cco 65% v cco v cco + 0.300 0.450 v cco ?0.450 note 5 note 5 lvcmos25 ?0.300 0.7 1.700 v cco + 0.300 0.400 v cco ?0.400 note 4 note 4 lvcmos33 ?0.300 0.8 2.000 3.450 0.400 v cco ?0.400 note 4 note 4 lvttl ?0.300 0.8 2.000 3.450 0.400 2.400 note 5 note 5 mobile_ddr ?0.300 20% v cco 80% v cco v cco + 0.300 10% v cco 90% v cco 0.10 ?0.10 pci33_3 ?0.400 30% v cco 50% v cco v cco + 0.500 10% v cco 90% v cco 1.50 ?0.50 sstl135 ?0.300 v ref ? 0.090 v ref + 0.090 v cco +0.300 v cco /2?0.150 v cco /2 + 0.150 13.00 ?13.00 sstl135_r ?0.300 v ref ? 0.090 v ref + 0.090 v cco +0.300 v cco /2?0.150 v cco /2 + 0.150 8.90 ?8.90 sstl15 ?0.300 v ref ? 0.100 v ref + 0.100 v cco +0.300 v cco /2?0.175 v cco /2 + 0.175 13.00 ?13.00 sstl15_r ?0.300 v ref ? 0.100 v ref + 0.100 v cco +0.300 v cco /2?0.175 v cco /2 + 0.175 8.90 ?8.90 sstl18_i ?0.300 v ref ? 0.125 v ref + 0.125 v cco +0.300 v cco /2?0.470 v cco /2 + 0.470 8.00 ?8.00 s e n d f e e d b a c k
artix-7 fpgas data sheet: dc and ac switching characteristics ds181 (v1.21) september 27, 2016 www.xilinx.com product specification 9 sstl18_ii ?0.300 v ref ? 0.125 v ref + 0.125 v cco +0.300 v cco /2?0.600 v cco /2 + 0.600 13.40 ?13.40 notes: 1. tested according to relevant specifications. 2. 3.3v and 2.5v standards are only supported in hr i/o banks. 3. supported drive strengths of 4, 8, or 12 ma in hr i/o banks. 4. supported drive strengths of 4, 8, 12, or 16 ma in hr i/o banks. 5. supported drive strengths of 4, 8, 12, 16, or 24 ma in hr i/o banks. 6. for detailed interface specific dc voltage levels, see 7 series fpgas selectio resources user guide ( ug471 ). table 9: differential selectio dc input and output levels i/o standard v icm (1) v id (2) v ocm (3) v od (4) v, min v, typ v, max v, min v, typ v, max v, min v, typ v, max v, min v, typ v, max blvds_25 0.300 1.200 1.425 0.100 ? ? ? 1.250 ? note 5 mini_lvds_25 0.300 1.200 v ccaux 0.200 0.400 0.600 1.000 1.200 1.400 0.300 0.450 0.600 ppds_25 0.200 0.900 v ccaux 0.100 0.250 0.400 0.500 0.950 1.400 0.100 0.250 0.400 rsds_25 0.300 0.900 1.500 0.100 0.350 0.600 1.000 1.200 1.400 0.100 0.350 0.600 tmds_33 2.700 2.965 3.230 0.150 0.675 1.200 v cco ?0.405 v cco ?0.300 v cco ?0.190 0.400 0.600 0.800 notes: 1. v icm is the input common mode voltage. 2. v id is the input differential voltage (q ? q ). 3. v ocm is the output common mode voltage. 4. v od is the output differential voltage (q ? q ). 5. v od for blvds will vary significantly depending on topology and loading. table 10: complementary differential selectio dc input and output levels i/o standard v icm (1) v id (2) v ol (3) v oh (4) i ol i oh v, min v,typ v, max v,min v, max v, max v, min ma, max ma, min diff_hstl_i 0.300 0.750 1.125 0.100 ? 0.400 v cco ?0.400 8.00 ?8.00 diff_hstl_i_18 0.300 0. 900 1.425 0.100 ? 0.400 v cco ?0.400 8.00 ?8.00 diff_hstl_ii 0.300 0.75 0 1.125 0.100 ? 0.400 v cco ?0.400 16.00 ?16.00 diff_hstl_ii_18 0.300 0.900 1.425 0.100 ? 0.400 v cco ?0.400 16.00 ?16.00 diff_hsul_12 0.300 0.600 0.850 0.100 ? 20% v cco 80% v cco 0.100 ?0.100 diff_mobile_ddr 0.300 0.900 1.425 0.100 ? 10% v cco 90% v cco 0.100 ?0.100 diff_sstl135 0.300 0.675 1.000 0.100 ? (v cco /2) ? 0.150 (v cco /2) + 0.150 13.0 ?13.0 diff_sstl135_r 0.300 0.675 1.000 0.100 ? (v cco /2) ? 0.150 (v cco /2) + 0.150 8.9 ?8.9 diff_sstl15 0.300 0.750 1.125 0.100 ? (v cco /2) ? 0.175 (v cco /2) + 0.175 13.0 ?13.0 diff_sstl15_r 0.300 0.750 1.125 0.100 ? (v cco /2) ? 0.175 (v cco /2) + 0.175 8.9 ?8.9 diff_sstl18_i 0.300 0.900 1.425 0.100 ? (v cco /2) ? 0.470 (v cco /2) + 0.470 8.00 ?8.00 diff_sstl18_ii 0.300 0.900 1.425 0.100 ? (v cco /2) ? 0.600 (v cco /2) + 0.600 13.4 ?13.4 notes: 1. v icm is the input common mode voltage. 2. v id is the input differential voltage (q ? q ). 3. v ol is the single-ended low-output voltage. 4. v oh is the single-ended high-output voltage. table 8: selectio dc input and output levels (1)(2) (cont?d) i/o standard v il v ih v ol v oh i ol i oh v, min v, max v, min v, max v, max v, min ma, max ma, min s e n d f e e d b a c k
artix-7 fpgas data sheet: dc and ac switching characteristics ds181 (v1.21) september 27, 2016 www.xilinx.com product specification 10 lvds dc specifications (lvds_25) table 11: lvds_25 dc specifications (1) symbol dc parameter conditions min typ max units v cco supply voltage 2.375 2.500 2.625 v v oh output high voltage for q and q r t = 100 across q and q signals ? ? 1.675 v v ol output low voltage for q and q r t = 100 across q and q signals 0.700 ? ? v v odiff differential output voltage: (q ? q ), q = high (q ?q), q =high r t = 100 across q and q signals 247 350 600 mv v ocm output common-mode voltage r t = 100 across q and q signals 1.000 1.250 1.425 v v idiff differential input voltage: (q ? q ), q = high (q ?q), q =high 100 350 600 mv v icm input common-mode voltage 0.300 1.200 1.500 v notes: 1. differential inputs for lvds_25 can be placed in banks with v cco levels that are different from the required level for outputs. consult the 7 series fpgas selectio resources user guide ( ug471 ) for more information. s e n d f e e d b a c k
artix-7 fpgas data sheet: dc and ac switching characteristics ds181 (v1.21) september 27, 2016 www.xilinx.com product specification 11 ac switching characteristics all values represented in this data sheet are based on the sp eed specifications from the ise? design suite 14.7 and vivado? design suite 2016.3 as outlined in table 12 . switching characteristics are specified on a per-speed-grade basis and can be designated as advance, preliminary, or production. each designatio n is defined as follows: advance product specification these specifications are based on simulations only and are typi cally available soon after device design specifications are frozen. although speed grades with this designation are considered relatively stab le and conservative, some under-reporting might still occur. preliminary produc t specification these specifications are based on complete es (engineering sample) silicon characterization. devices and speed grades with this designation are intended to give a be tter indication of the expected performanc e of production silicon. the probability of under-reporting delays is greatly reduced as compared to advance data. production product specification these specifications are released once enough production silicon of a particular device family member has been characterized to provide full correlation between specifications and devices over numerous production lots. there is no under-reporting of delays, and customers receive formal notification of any subs equent changes. typically, the slowest speed grades transition to production before faster speed grades. testing of ac switching characteristics internal timing parameters are derived from measuring inte rnal test patterns. all ac switching characteristics are representative of worst-case supply volt age and junction temperature conditions. for more specific, more precise, and worst-case guaranteed data , use the values reported by th e static timing analyzer and back-annotate to the simulation net list. unless ot herwise noted, values apply to all artix-7 fpgas. table 12: artix-7 fpga speed specification version by device version in: typical v ccint device ise 14.7 vivado 2016.3 ( table 2 ) n/a 1.15 1.0v xc7a12t, xc7a15t, xc7a25t, xc7a35t, xc7a50t, xc7a75t n/a 1.15 0.95v xc7a12t, xc7a15t, xc7a25t, xc7a35t, xc7a50t, xc7a75t, xc7a100t, xc7a200t n/a 1.10 0.9v xc7a12t, xc7a15t, xc7a25t, xc7a35t, xc7a50t, xc7a75t 1.10 1.15 1.0v xc7a100t, xc7a200t 1.07 1.10 0.9v xc7a100t, xc7a200t n/a 1.11 1.0v xa7a15t, xa7a35t, xa7a50t, xa7a75t 1.07 1.11 1.0v xa7a100t 1.06 1.11 1.0v xq7a100t, xq7a200t n/a 1.11 1.0v xq7a50t s e n d f e e d b a c k
artix-7 fpgas data sheet: dc and ac switching characteristics ds181 (v1.21) september 27, 2016 www.xilinx.com product specification 12 speed grade designations since individual family members are prod uced at different times, the migration from one category to another depends completely on the status of the fabrication process for each device. table 13 correlates the current status of each artix-7 device on a per speed grade basis. production silicon and software status in some cases, a particular family memb er (and speed grade) is released to production before a speed specification is released with the correct label (advance, preliminary, producti on). any labeling discrepancies are corrected in subsequent speed specification releases. table 14 lists the production released artix-7 device, speed grade, and the minimum corresponding supported speed specification version and software revision s. the software and speed specifications listed are the minimum releases required for production. all subsequent releases of software and speed specifications are valid. table 13: artix-7 device speed grade designations device speed grade designations advance preliminary production xc7a12t -3, -2, -1, and -1li (0.95v) xc7a15t -3, -2, -2le (1.0v), -1, -1li (0.95v), and -2le (0.9v) xc7a25t -3, -2, -1, and -1li (0.95v) xc7a35t -3, -2, -2le (1.0v), -1, -1li (0.95v), and -2le (0.9v) xc7a50t -3, -2, -2le (1.0v), -1, -1li (0.95v), and -2le (0.9v) xc7a75t -3, -2, -2le (1.0v), -1, -1li (0.95v), and -2le (0.9v) xc7a100t -3, -2, -2le (1.0v), -1, -1li (0. 95v), and -2le (0.9v) xc7a200t -3, -2, -2le (1.0v), -1, -1li (0. 95v), and -2le (0.9v) xa7a15t -2i, -1i, and -1q xa7a35t -2i, -1i, and -1q xa7a50t -2i, -1i, and -1q xa7a75t -2i, -1i, and -1q xa7a100t -2i, -1i, and -1q xq7a50t -2i, -1i, -1li (0.95v), and -1m xq7a100t -2i, -1i, -1li (0.95v), and -1m xq7a200t -2i, -1i, -1li (0.95v), and -1m table 14: artix-7 device production software and speed specification release device speed grade 1.0v 0.95v 0.9v -3 -2 -2le -1 -1q -1m -1li -2le xc7a12t n/a n/a xc7a15t vivado tools 2014.4 v1.14 n/a n/a vivado tools 2014.4 v1.14 vivado tools 2014.4 v1.10 xc7a25t n/a n/a xc7a35t vivado tools 2013.4 v1.11 n/a n/a vivado tools 2014.4 v1.14 vivado tools 2013.4 v1.08 xc7a50t vivado tools 2013.4 v1.11 n/a n/a vivado tools 2014.4 v1.14 vivado tools 2013.4 v1.08 xc7a75t vivado tools 2013.3 v1.10 n/a n/a vivado tools 2014.4 v1.14 vivado tools 2013.3 v1.07 s e n d f e e d b a c k
artix-7 fpgas data sheet: dc and ac switching characteristics ds181 (v1.21) september 27, 2016 www.xilinx.com product specification 13 selecting the correct speed grade and voltage in the vivado tools it is important to select the correct devi ce speed grade and voltage in the vivado to ols for the device that you are selecting. to select the 1.0v speed specificatio ns in the vivado tools, select the artix-7 , xa artix-7 , or defense grade artix-7q sub-family, and then select the part name that is the devi ce name followed by the pack age name followed by the speed grade. for example, select the xc7a100tfgg676-3 part name for the xc7a100t device in the fgg676 package and -3 (1.0v) speed grade or select the xc7a100tfgg676-2l part name for the xc7a100t device in the fgg676 package and -2le (1.0v) speed grade. to select the -1li (0.95v) speed specific ations in the vivado tools, select the artix-7 sub-family and then select the part name that is the device name followed by an ?i? followed by the package name followed by the speed grade. for example, select the xc7a100tifgg676-1l part name for the xc7a100t device in the fgg676 package and -1li (0.95v) speed grade. the -1li (0.95v) speed specifications are not supported in the ise tools. to select the -2le (0.9v) speed specifications in the vivado tools, select the artix-7 low voltage sub-family and then select the part name that is the devi ce name followed by an ?l? followed by the package name followed by the speed grade. for example, select the xc7a100tlfgg676-2l part name for the xc7a100t device in th e fgg676 package and -2le (0.9v) speed grade. a similar part naming co nvention applies to the speed specifications selection in the ise tools for supported devices. see table 14 for the subset of 7 series fp gas supported in the ise tools. xc7a100t ise tools 14.4 or vivado tools 2012.4 with the 14.4/2012.4 device pack v1.07 n/a n/a vivado tools 2014.4 v1.14 ise tools 14.5 or vivado tools 2013.1 v1.05 xc7a200t ise tools 14.4 or vivado tools 2012.4 with the 14.4/2012.4 device pack v1.07 n/a n/a vivado tools 2014.4 v1.14 xa7a15t n/a vivado tools 2014.4 v1.14 n/a vivado tools 2014.4 v1.14 n/a n/a n/a xa7a35t n/a vivado tools 2014.1 v1.09 n/a vivado tools 2014.1 v1.09 n/a n/a n/a xa7a50t n/a vivado tools 2014.1 v1.09 n/a vivado tools 2014.1 v1.09 n/a n/a n/a xa7a75t n/a vivado tools 2014.1 v1.09 n/a vivado tools 2014.1 v1.09 n/a n/a n/a xa7a100t n/a ise tools 14.5 or vivado tools 2013.1 v1.05 n/a ise tools 14.5 or vivado tools 2013.1 v1.05 ise tools 14.6 or vivado tools 2013.2 v1.06 n/a n/a n/a xq7a50t n/a vivado tools 2014.2 v1.08 n/a vivado tools 2014.2 v1.08 n/a vivado tools 2014.2 v1.08 vivado tools 2015.4 v1.11 n/a xq7a100t n/a ise tools 14.5 or vivado tools 2013.1 v1.04 n/a ise tools 14.5 or vivado tools 2013.1 v1.04 n/a ise tools 14.6 or vivado tools 2013.2 v1.05 vivado tools 2015.4 v1.11 n/a xq7a200t n/a ise tools 14.5 or vivado tools 2013.1 v1.04 n/a ise tools 14.5 or vivado tools 2013.1 v1.04 n/a ise tools 14.6 or vivado tools 2013.2 v1.05 vivado tools 2015.4 v1.11 n/a notes: 1. blank entries indicate a device and/or speed grade in advance or preliminary status. table 14: artix-7 device production software and speed specification release (cont?d) device speed grade 1.0v 0.95v 0.9v -3 -2 -2le -1 -1q -1m -1li -2le s e n d f e e d b a c k
artix-7 fpgas data sheet: dc and ac switching characteristics ds181 (v1.21) september 27, 2016 www.xilinx.com product specification 14 performance characteristics this section provides the performance characteristics of some common function s and designs implemented in artix-7 devices. the numbers reported here are wors t-case values; they have al l been fully characterized. these values are subject to the same guidelines as the ac switching characteristics, page 11 . table 15: networking applications interface performances description speed grade units 1.0v 0.95v 0.9v -3 -2/-2le -1 -1li -2le sdr lvds transmitter (using oserdes; data_width = 4 to 8) 680 680 600 600 600 mb/s ddr lvds transmitter (using oserdes; data_width = 4 to 14) 1250 1250 950 950 950 mb/s sdr lvds receiver (sfi-4.1) (1) 680 680 600 600 600 mb/s ddr lvds receiver (spi-4.2) (1) 1250 1250 950 950 950 mb/s notes: 1. lvds receivers are typically bounded with certain applications where specific dynamic phase-alignment (dpa) algorithms domina te deterministic performance. table 16: maximum physical interface (phy) rate for memory interfaces ip available with the memory interface generator (1)(2) memory standard speed grade units 1.0v 0.95v 0.9v -3 -2/-2le -1 -1q/-1m -1li -2le 4:1 memory controllers ddr3 1066 800 800 667 800 800 mb/s ddr3l 800 800 667 n/a 667 667 mb/s ddr2 800 800 667 533 667 667 mb/s 2:1 memory controllers ddr3 800 700 620 620 620 620 mb/s ddr3l 800 700 620 n/a 620 620 mb/s ddr2 800 700 620 533 620 620 mb/s lpddr2 667 667 533 400 533 533 mb/s notes: 1. v ref tracking is required. for more information, see 7 series fpgas memory interface solutions user guide ( ug586 ). 2. when using the internal v ref , the maximum data rate is 800 mb/s (400 mhz). s e n d f e e d b a c k
artix-7 fpgas data sheet: dc and ac switching characteristics ds181 (v1.21) september 27, 2016 www.xilinx.com product specification 15 iob pad input/output/3-state table 17 summarizes the values of standard-specific data input dela y adjustments, output delays terminating at pads (based on standard) and 3-state delays. ?t iopi is described as the delay from iob pad through the inpu t buffer to the i-pin of an iob pad. the delay varies depending on the capability of the selectio input buffer. ?t ioop is described as the delay from the o pin to the iob pad through the output buffer of an iob pad. the delay varies depending on the capability of the selectio output buffer. ?t iotp is described as the delay from the t pin to the iob pad through the output buffer of an iob pad, when 3-state is disabled. the delay varies depending on the selectio capability of the output buffer. in hr i/o banks, the in_term termination turn-on time is always faster than t iotp when the intermdisable pin is used. table 17: iob high range (hr) sw itching characteristics i/o standard t iopi t ioop t iotp units speed grade speed grade speed grade 1.0v 0.95v 0.9v 1.0v 0.95v 0.9v 1.0v 0.95v 0.9v -3 -2/ -2le -1 -1q/ -1m -1li -2le -3 -2/ -2le -1 -1q/ -1m -1li -2le -3 -2/ -2le -1 -1q/ -1m -1li -2le lvttl_s4 1.26 1.34 1.41 1.53 1.41 1.58 3.80 3.93 4.18 4.18 4.18 4.41 3.82 3.96 4.20 4.20 4.20 4.05 ns lvttl_s8 1.26 1.34 1.41 1.53 1.41 1.58 3.54 3.66 3.92 3.92 3.92 4.15 3.56 3.69 3.93 3.93 3.93 3.78 ns lvttl_s12 1.26 1.34 1.41 1.53 1.41 1.58 3.52 3.65 3.90 3.90 3.90 4.13 3.54 3.68 3.91 3.91 3.91 3.77 ns lvttl_s16 1.26 1.34 1.41 1.53 1.41 1.58 3.07 3.19 3.45 3.45 3.45 3.68 3.09 3.22 3.46 3.46 3.46 3.31 ns lvttl_s24 1.26 1.34 1.41 1.53 1.41 1.58 3.29 3.41 3.67 3.67 3.67 3.90 3.31 3.44 3.68 3.68 3.68 3.53 ns lvttl_f4 1.26 1.34 1.41 1.53 1.41 1.58 3.26 3.38 3.64 3.64 3.64 3.86 3.28 3.41 3.65 3.65 3.65 3.50 ns lvttl_f8 1.26 1.34 1.41 1.53 1.41 1.58 2.74 2.87 3.12 3.12 3.12 3.35 2.76 2.90 3.13 3.13 3.13 2.99 ns lvttl_f12 1.26 1.34 1.41 1.53 1.41 1.58 2.73 2.85 3.10 3.10 3.10 3.33 2.74 2.88 3.12 3.12 3.12 2.97 ns lvttl_f16 1.26 1.34 1.41 1.53 1.41 1.58 2.56 2.68 2.93 2.93 2.93 3.16 2.57 2.71 2.95 2.95 2.95 2.80 ns lvttl_f24 1.26 1.34 1.41 1.53 1.41 1.58 2.52 2.65 2.90 3.23 2.90 3.22 2.54 2.68 2.91 3.24 2.91 2.86 ns lvds_25 0.73 0.81 0.88 0.89 0.88 0.90 1.29 1.41 1.67 1.67 1.67 1.86 1.31 1.44 1.68 1.68 1.68 1.50 ns mini_lvds_25 0.73 0.81 0.88 0.89 0.88 0.90 1.27 1.40 1.65 1.65 1.65 1.88 1.29 1.43 1.66 1.66 1.66 1.52 ns blvds_25 0.73 0.81 0.88 0.88 0.88 0.90 1.84 1.96 2.21 2.76 2.21 2.44 1.85 1.99 2.23 2.77 2.23 2.08 ns rsds_25 (point to point) 0.73 0.81 0.88 0.89 0.88 0.90 1.27 1.40 1.65 1.65 1.65 1.88 1.29 1.43 1.66 1.66 1.66 1.52 ns ppds_25 0.73 0.81 0.88 0.89 0.88 0.90 1.29 1.41 1.67 1.67 1.67 1.88 1.31 1.44 1.68 1.68 1.68 1.52 ns tmds_33 0.73 0.81 0.88 0.92 0.88 0.90 1.41 1.54 1.79 1.79 1.79 1.99 1.43 1.57 1.80 1.80 1.80 1.63 ns pci33_3 1.24 1.32 1.39 1.52 1.39 1.57 3.10 3.22 3.48 3.48 3.48 3.71 3.12 3.25 3.49 3.49 3.49 3.34 ns hsul_12_s 0.67 0.75 0.82 0.88 0.82 0.87 1.81 1.93 2.18 2.18 2.18 2.41 1.82 1.96 2.20 2.20 2.20 2.05 ns hsul_12_f 0.67 0.75 0.82 0.88 0.82 0.87 1.29 1.41 1.67 1.67 1.67 1.90 1.31 1.44 1.68 1.68 1.68 1.53 ns diff_hsul_ 12_s 0.68 0.76 0.83 0.86 0.83 0.88 1.81 1.93 2.18 2.18 2.18 2.21 1.82 1.96 2.20 2.20 2.20 1.84 ns diff_hsul_ 12_f 0.68 0.76 0.83 0.86 0.83 0.88 1.29 1.41 1.67 1.67 1.67 1.79 1.31 1.44 1.68 1.68 1.68 1.42 ns mobile_ ddr_s 0.76 0.84 0.91 0.91 0.91 0.96 1.68 1.80 2.06 2.06 2.06 2.24 1.70 1.83 2.07 2.07 2.07 1.88 ns mobile_ ddr_f 0.76 0.84 0.91 0.91 0.91 0.96 1.38 1.51 1.76 1.76 1.76 1.97 1.40 1.54 1.77 1.77 1.77 1.61 ns diff_mobile_ ddr_s 0.70 0.78 0.85 0.85 0.85 0.87 1.70 1.82 2.07 2.07 2.07 2.24 1.71 1.85 2.09 2.09 2.09 1.88 ns diff_mobile_ ddr_f 0.70 0.78 0.85 0.85 0.85 0.87 1.45 1.57 1.82 1.82 1.82 2.00 1.46 1.60 1.84 1.84 1.84 1.64 ns s e n d f e e d b a c k
artix-7 fpgas data sheet: dc and ac switching characteristics ds181 (v1.21) september 27, 2016 www.xilinx.com product specification 16 hstl_i_s 0.67 0.75 0.82 0.86 0.82 0.87 1.62 1.74 1.99 1.99 1.99 2.19 1.63 1.77 2.01 2.01 2.01 1.83 ns hstl_ii_s 0.65 0.73 0.80 0.86 0.80 0.85 1.41 1.54 1.79 1.79 1.79 1.99 1.43 1.57 1.80 1.81 1.80 1.63 ns hstl_i_18_s 0.67 0.75 0.82 0.88 0.82 0.87 1.29 1.41 1.67 1.67 1.67 1.86 1.31 1.44 1.68 1.68 1.68 1.50 ns hstl_ii_18_s 0.66 0.75 0.81 0.88 0.81 0.87 1.41 1.54 1.79 1.79 1.79 1.97 1.43 1.57 1.80 1.80 1.80 1.61 ns diff_hstl_i_s 0.68 0.76 0.83 0.86 0.83 0.85 1.59 1.71 1.96 1.96 1.96 2.13 1.60 1.74 1.98 1.98 1.98 1.77 ns diff_hstl_ ii_s 0.68 0.76 0.83 0.86 0.83 0.85 1.51 1.63 1.88 1.88 1.88 2.07 1.52 1.66 1.90 1.90 1.90 1.70 ns diff_hstl_ i_18_s 0.71 0.79 0.86 0.86 0.86 0.87 1.38 1.51 1.76 1.76 1.76 1.96 1.40 1.54 1.77 1.77 1.77 1.59 ns diff_hstl_ ii_18_s 0.70 0.78 0.85 0.88 0.85 0.87 1.46 1.58 1.84 1.84 1.84 2.00 1.48 1.61 1.85 1.85 1.85 1.64 ns hstl_i_f 0.67 0.75 0.82 0.86 0.82 0.87 1.10 1.22 1.48 1.49 1.48 1.69 1.12 1.25 1.49 1.51 1.49 1.33 ns hstl_ii_f 0.65 0.73 0.80 0.86 0.80 0.85 1.12 1.24 1.49 1.49 1.49 1.71 1.13 1.27 1.51 1.51 1.51 1.34 ns hstl_i_18_f 0.67 0.75 0.82 0.88 0.82 0.87 1.13 1.26 1.51 1.54 1.51 1.72 1.15 1.29 1.52 1.56 1.52 1.36 ns hstl_ii_18_f 0.66 0.75 0.81 0.88 0.81 0.87 1.12 1.24 1.49 1.51 1.49 1.71 1.13 1.27 1.51 1.52 1.51 1.34 ns diff_hstl_i_f 0.68 0.76 0.83 0.86 0.83 0.85 1.18 1.30 1.56 1.56 1.56 1.77 1.20 1.33 1.57 1.57 1.57 1.41 ns diff_hstl_ ii_f 0.68 0.76 0.83 0.86 0.83 0.85 1.21 1.33 1.59 1.59 1.59 1.77 1.23 1.36 1.60 1.60 1.60 1.41 ns diff_hstl_ i_18_f 0.71 0.79 0.86 0.86 0.86 0.87 1.21 1.33 1.59 1.59 1.59 1.77 1.23 1.36 1.60 1.60 1.60 1.41 ns diff_hstl_ ii_18_f 0.70 0.78 0.85 0.88 0.85 0.87 1.21 1.33 1.59 1.59 1.59 1.77 1.23 1.36 1.60 1.60 1.60 1.41 ns lvcmos33_s4 1.26 1.34 1.41 1.52 1.41 1.62 3.80 3.93 4.18 4.18 4.18 4.41 3.82 3.96 4.20 4.20 4.20 4.05 ns lvcmos33_s8 1.26 1.34 1.41 1.52 1.41 1.62 3.52 3.65 3.90 3.90 3.90 4.13 3.54 3.68 3.91 3.91 3.91 3.77 ns lvcmos33_s12 1.26 1.34 1.41 1.52 1.41 1.62 3.09 3.21 3.46 3.46 3.46 3.69 3.10 3.24 3.48 3.48 3.48 3.33 ns lvcmos33_s16 1.26 1.34 1.41 1.52 1.41 1.62 3.40 3.52 3.77 3.78 3.77 4.00 3.42 3.55 3.79 3.79 3.79 3.64 ns lvcmos33_f4 1.26 1.34 1.41 1.52 1.41 1.62 3.26 3.38 3.64 3.64 3.64 3.86 3.28 3.41 3.65 3.65 3.65 3.50 ns lvcmos33_f8 1.26 1.34 1.41 1.52 1.41 1.62 2.74 2.87 3.12 3.12 3.12 3.35 2.76 2.90 3.13 3.13 3.13 2.99 ns lvcmos33_f12 1.26 1.34 1.41 1.52 1.41 1.62 2.56 2.68 2.93 2.93 2.93 3.16 2.57 2.71 2.95 2.95 2.95 2.80 ns lvcmos33_f16 1.26 1.34 1.41 1.52 1.41 1.62 2.56 2.68 2.93 3.06 2.93 3.16 2.57 2.71 2.95 3.07 2.95 2.80 ns lvcmos25_s4 1.12 1.20 1.27 1.38 1.27 1.43 3.13 3.26 3.51 3.51 3.51 3.72 3.15 3.29 3.52 3.52 3.52 3.36 ns lvcmos25_s8 1.12 1.20 1.27 1.38 1.27 1.43 2.88 3.01 3.26 3.26 3.26 3.49 2.90 3.04 3.27 3.27 3.27 3.13 ns lvcmos25_s12 1.12 1.20 1.27 1.38 1.27 1.43 2.48 2.60 2.85 2.85 2.85 3.08 2.49 2.63 2.87 2.87 2.87 2.72 ns lvcmos25_s16 1.12 1.20 1.27 1.38 1.27 1.43 2.82 2.94 3.20 3.20 3.20 3.43 2.84 2.97 3.21 3.21 3.21 3.06 ns lvcmos25_f4 1.12 1.20 1.27 1.38 1.27 1.43 2.74 2.87 3.12 3.12 3.12 3.35 2.76 2.90 3.13 3.13 3.13 2.99 ns lvcmos25_f8 1.12 1.20 1.27 1.38 1.27 1.43 2.18 2.30 2.56 2.56 2.56 2.79 2.20 2.33 2.57 2.57 2.57 2.42 ns lvcmos25_f12 1.12 1.20 1.27 1.38 1.27 1.43 2.16 2.29 2.54 2.54 2.54 2.77 2.18 2.32 2.55 2.56 2.55 2.41 ns lvcmos25_f16 1.12 1.20 1.27 1.38 1.27 1.43 2.01 2.13 2.39 2.63 2.39 2.61 2.03 2.16 2.40 2.65 2.40 2.25 ns lvcmos18_s4 0.74 0.83 0.89 0.97 0.89 0.94 1.62 1.74 1.99 1.99 1.99 2.19 1.63 1.77 2.01 2.01 2.01 1.83 ns lvcmos18_s8 0.74 0.83 0.89 0.97 0.89 0.94 2.18 2.30 2.56 2.56 2.56 2.79 2.20 2.33 2.57 2.57 2.57 2.42 ns lvcmos18_s12 0.74 0.83 0.89 0.97 0.89 0.94 2.18 2.30 2.56 2.56 2.56 2.79 2.20 2.33 2.57 2.57 2.57 2.42 ns table 17: iob high range (hr) switching characteristics (cont?d) i/o standard t iopi t ioop t iotp units speed grade speed grade speed grade 1.0v 0.95v 0.9v 1.0v 0.95v 0.9v 1.0v 0.95v 0.9v -3 -2/ -2le -1 -1q/ -1m -1li -2le -3 -2/ -2le -1 -1q/ -1m -1li -2le -3 -2/ -2le -1 -1q/ -1m -1li -2le s e n d f e e d b a c k
artix-7 fpgas data sheet: dc and ac switching characteristics ds181 (v1.21) september 27, 2016 www.xilinx.com product specification 17 lvcmos18_s16 0.74 0.83 0.89 0.97 0.89 0.94 1.52 1.65 1.90 1.90 1.90 2.13 1.54 1.68 1.91 1.91 1.91 1.77 ns lvcmos18_s24 0.74 0.83 0.89 0.97 0.89 0.94 1.60 1.72 1.98 2.40 1.98 2.21 1.62 1.75 1.99 2.41 1.99 1.84 ns lvcmos18_f4 0.74 0.83 0.89 0.97 0.89 0.94 1.45 1.57 1.82 1.82 1.82 2.05 1.46 1.60 1.84 1.84 1.84 1.69 ns lvcmos18_f8 0.74 0.83 0.89 0.97 0.89 0.94 1.68 1.80 2.06 2.06 2.06 2.29 1.70 1.83 2.07 2.07 2.07 1.92 ns lvcmos18_f12 0.74 0.83 0.89 0.97 0.89 0.94 1.68 1.80 2.06 2.06 2.06 2.29 1.70 1.83 2.07 2.07 2.07 1.92 ns lvcmos18_f16 0.74 0.83 0.89 0.97 0.89 0.94 1.40 1.52 1.77 1.78 1.77 2.00 1.42 1.55 1.79 1.79 1.79 1.64 ns lvcmos18_f24 0.74 0.83 0.89 0.97 0.89 0.94 1.34 1.46 1.71 2.28 1.71 1.94 1.35 1.49 1.73 2.29 1.73 1.58 ns lvcmos15_s4 0.77 0.86 0.93 0.96 0.93 0.98 2.05 2.18 2.43 2.43 2.43 2.50 2.07 2.21 2.45 2.45 2.45 2.14 ns lvcmos15_s8 0.77 0.86 0.93 0.96 0.93 0.98 2.09 2.21 2.46 2.46 2.46 2.69 2.10 2.24 2.48 2.48 2.48 2.33 ns lvcmos15_s12 0.77 0.86 0.93 0.96 0.93 0.98 1.59 1.71 1.96 1.96 1.96 2.19 1.60 1.74 1.98 1.98 1.98 1.83 ns lvcmos15_s16 0.77 0.86 0.93 0.96 0.93 0.98 1.59 1.71 1.96 1.96 1.96 2.19 1.60 1.74 1.98 1.98 1.98 1.83 ns lvcmos15_f4 0.77 0.86 0.93 0.96 0.93 0.98 1.85 1.97 2.23 2.23 2.23 2.27 1.87 2.00 2.24 2.24 2.24 1.91 ns lvcmos15_f8 0.77 0.86 0.93 0.96 0.93 0.98 1.60 1.72 1.98 1.98 1.98 2.21 1.62 1.75 1.99 1.99 1.99 1.84 ns lvcmos15_f12 0.77 0.86 0.93 0.96 0.93 0.98 1.35 1.47 1.73 1.73 1.73 1.96 1.37 1.50 1.74 1.74 1.74 1.59 ns lvcmos15_f16 0.77 0.86 0.93 0.96 0.93 0.98 1.34 1.46 1.71 2.07 1.71 1.94 1.35 1.49 1.73 2.09 1.73 1.58 ns lvcmos12_s4 0.87 0.95 1.02 1.19 1.02 1.08 2.57 2.69 2.95 2.95 2.95 3.18 2.59 2.72 2.96 2.96 2.96 2.81 ns lvcmos12_s8 0.87 0.95 1.02 1.19 1.02 1.08 2.09 2.21 2.46 2.46 2.46 2.69 2.10 2.24 2.48 2.48 2.48 2.33 ns lvcmos12_s12 0.87 0.95 1.02 1.19 1.02 1.08 1.79 1.91 2.17 2.17 2.17 2.40 1.81 1.94 2.18 2.18 2.18 2.03 ns lvcmos12_f4 0.87 0.95 1.02 1.19 1.02 1.08 1.98 2.10 2.35 2.35 2.35 2.58 1.99 2.13 2.37 2.37 2.37 2.22 ns lvcmos12_f8 0.87 0.95 1.02 1.19 1.02 1.08 1.54 1.66 1.92 1.92 1.92 2.15 1.56 1.69 1.93 1.93 1.93 1.78 ns lvcmos12_f12 0.87 0.95 1.02 1.19 1.02 1.08 1.38 1.51 1.76 1.76 1.76 1.97 1.40 1.54 1.77 1.77 1.77 1.61 ns sstl135_s 0.67 0.75 0.82 0.88 0.82 0.87 1.35 1.47 1.73 1.73 1.73 1.93 1.37 1.50 1.74 1.74 1.74 1.56 ns sstl15_s 0.60 0.68 0.75 0.75 0.75 0.80 1.30 1.43 1.68 1.71 1.68 1.88 1.32 1.46 1.69 1.73 1.69 1.52 ns sstl18_i_s 0.67 0.75 0.82 0.86 0.82 0.87 1.67 1.79 2.04 2.04 2.04 2.24 1.68 1.82 2.06 2.06 2.06 1.88 ns sstl18_ii_s 0.67 0.75 0.82 0.88 0.82 0.85 1.31 1.43 1.68 1.68 1.68 1.91 1.32 1.46 1.70 1.70 1.70 1.55 ns diff_sstl135_ s 0.68 0.76 0.83 0.88 0.83 0.87 1.35 1.47 1.73 1.73 1.73 1.93 1.37 1.50 1.74 1.74 1.74 1.56 ns diff_sstl15_ s 0.68 0.76 0.83 0.88 0.83 0.87 1.30 1.43 1.68 1.71 1.68 1.88 1.32 1.46 1.69 1.73 1.69 1.52 ns diff_sstl18 _i_s 0.71 0.79 0.86 0.88 0.86 0.87 1.68 1.80 2.06 2.06 2.06 2.24 1.70 1.83 2.07 2.07 2.07 1.88 ns diff_sstl18 _ii_s 0.71 0.79 0.86 0.88 0.86 0.87 1.38 1.51 1.76 1.76 1.76 1.94 1.40 1.54 1.77 1.77 1.77 1.58 ns table 17: iob high range (hr) switching characteristics (cont?d) i/o standard t iopi t ioop t iotp units speed grade speed grade speed grade 1.0v 0.95v 0.9v 1.0v 0.95v 0.9v 1.0v 0.95v 0.9v -3 -2/ -2le -1 -1q/ -1m -1li -2le -3 -2/ -2le -1 -1q/ -1m -1li -2le -3 -2/ -2le -1 -1q/ -1m -1li -2le s e n d f e e d b a c k
artix-7 fpgas data sheet: dc and ac switching characteristics ds181 (v1.21) september 27, 2016 www.xilinx.com product specification 18 table 18 specifies the values of t iotphz and t ioibufdisable . t iotphz is described as the delay from the t pin to the iob pad through the output buffer of an iob pad, when 3-state is enabled (i.e., a high impedance state). t ioibufdisable is described as the iob delay from ibufdisable to o output. in hr i/o banks, the internal in_term terminatio n turn-off time is always faster than t iotphz when the intermdisable pin is used. i/o standard adjustment measurement methodology input delay measurements table 19 shows the test setup parameters used for measuring input delay. sstl135_f 0.67 0.75 0.82 0.88 0.82 0.87 1.12 1.24 1.49 1.49 1.49 1.71 1.13 1.27 1.51 1.51 1.51 1.34 ns sstl15_f 0.60 0.68 0.75 0.75 0.75 0.80 1.07 1.19 1.45 1.45 1.45 1.68 1.09 1.22 1.46 1.46 1.46 1.31 ns sstl18_i_f 0.67 0.75 0.82 0.86 0.82 0.87 1.12 1.24 1.49 1.53 1.49 1.72 1.13 1.27 1.51 1.54 1.51 1.36 ns sstl18_ii_f 0.67 0.75 0.82 0.88 0.82 0.85 1.12 1.24 1.49 1.51 1.49 1.71 1.13 1.27 1.51 1.52 1.51 1.34 ns diff_sstl135 _f 0.68 0.76 0.83 0.88 0.83 0.87 1.12 1.24 1.49 1.49 1.49 1.71 1.13 1.27 1.51 1.51 1.51 1.34 ns diff_sstl15_f 0.68 0.76 0.83 0.88 0.83 0.87 1.07 1.19 1.45 1.45 1.45 1.68 1.09 1.22 1.46 1.46 1.46 1.31 ns diff_sstl18_i _f 0.71 0.79 0.86 0.88 0.86 0.87 1.23 1.35 1.60 1.60 1.60 1.80 1.24 1.38 1.62 1.62 1.62 1.44 ns diff_sstl18_ii _f 0.71 0.79 0.86 0.88 0.86 0.87 1.21 1.33 1.59 1.59 1.59 1.79 1.23 1.36 1.60 1.60 1.60 1.42 ns table 18: iob 3-state output switching characteristics symbol description speed grade units 1.0v 0.95v 0.9v -3 -2/-2le -1 -1q/-1m -1li -2le t iotphz t input to pad high-impedance 2.06 2.19 2.37 2.37 2.37 2.03 ns t ioibufdisable ibuf turn-on time from ibufdisable to o output 2.11 2.30 2.60 2.60 2.60 2.17 ns table 19: input delay measurement methodology description i /o standard attribute v l (1) v h (1) v meas (3)(5) v ref (2)(4) lvcmos, 1.2v lvcmos12 0.1 1.1 0.6 ? lvcmos, 1.5v lvcmos15 0.1 1.4 0.75 ? lvcmos, 1.8v lvcmos18 0.1 1.7 0.9 ? lvcmos, 2.5v lvcmos25 0.1 2.4 1.25 ? lvcmos, 3.3v lvcmos33 0.1 3.2 1.65 ? lvttl, 3.3v lvttl 0.1 3.2 1.65 ? mobile_ddr, 1.8v mobile_ddr 0.1 1.7 0.9 ? pci33, 3.3v pci33_3 0.1 3.2 1.65 ? hstl (high-speed transceiver logic), class i, 1.2v hstl_i_12 v ref ?0.5 v ref +0.5 v ref 0.60 table 17: iob high range (hr) switching characteristics (cont?d) i/o standard t iopi t ioop t iotp units speed grade speed grade speed grade 1.0v 0.95v 0.9v 1.0v 0.95v 0.9v 1.0v 0.95v 0.9v -3 -2/ -2le -1 -1q/ -1m -1li -2le -3 -2/ -2le -1 -1q/ -1m -1li -2le -3 -2/ -2le -1 -1q/ -1m -1li -2le s e n d f e e d b a c k
artix-7 fpgas data sheet: dc and ac switching characteristics ds181 (v1.21) september 27, 2016 www.xilinx.com product specification 19 hstl, class i & ii, 1.5v hstl_i, hstl_ii v ref ?0.65 v ref +0.65 v ref 0.75 hstl, class i & ii, 1.8v hstl_i_18, hstl_ii_18 v ref ?0.8 v ref +0.8 v ref 0.90 hsul (high-speed unterminated logic), 1.2v hsul_12 v ref ?0.5 v ref +0.5 v ref 0.60 sstl (stub terminated transceiver logic), 1.2v sstl12 v ref ?0.5 v ref +0.5 v ref 0.60 sstl, 1.35v sstl135, sstl135_r v ref ? 0.575 v ref + 0.575 v ref 0.675 sstl, 1.5v sstl15, sstl15_r v ref ?0.65 v ref +0.65 v ref 0.75 sstl, class i & ii, 1.8v sstl18_i, sstl18_ii v ref ?0.8 v ref +0.8 v ref 0.90 diff_mobile_ddr, 1.8v diff_mo bile_ddr 0.9 ? 0.125 0.9 + 0.125 0 (5) ? diff_hstl, class i, 1.2v di ff_hstl_i_12 0.6 ? 0.125 0.6 + 0.125 0 (5) ? diff_hstl, class i & ii,1.5v diff_hstl_i, diff_hstl_ii 0.75 ? 0.125 0.75 + 0.125 0 (5) ? diff_hstl, class i & ii, 1.8v diff_hstl_i_18, diff_hstl_ii_18 0.9 ? 0.125 0.9 + 0.125 0 (5) ? diff_hsul, 1.2v diff_hsul _12 0.6 ? 0.125 0.6 + 0.125 0 (5) ? diff_sstl135/dif f_sstl135_r, 1.35v diff_sstl135, diff_sstl135_r 0.675 ? 0.125 0.675 + 0.125 0 (5) ? diff_sstl15/diff _sstl15_r, 1.5v diff_sstl15, diff_sstl15_r 0.75 ? 0.125 0.75 + 0.125 0 (5) ? diff_sstl18_i/di ff_sstl18_ii, 1.8v diff_sstl18_i, diff_sstl18_ii 0.9 ? 0.125 0.9 + 0.125 0 (5) ? lvds_25, 2.5v lvds_2 5 1.2 ? 0.125 1.2 + 0.125 0 (5) ? blvds_25, 2.5v blvds_25 1.25 ? 0.125 1.25 + 0.125 0 (5) ? mini_lvds_25, 2.5v mini_lvds _25 1.25 ? 0.125 1.25 + 0.125 0 (5) ? ppds_25 ppds_25 1.25 ? 0.125 1.25 + 0.125 0 (5) ? rsds_25 rsds_25 1.25 ? 0.125 1.25 + 0.125 0 (5) ? tmds_33 tmds_33 3 ? 0.125 3 + 0.125 0 (5) ? notes: 1. input waveform switches between v l and v h . 2. measurements are made at typical, minimum, and maximum v ref values. reported delays reflect worst case of these measurements. v ref values listed are typical. 3. input voltage level from which measurement starts. 4. this is an input voltage reference that bears no relation to the v ref / v meas parameters found in ibis models and/or noted in figure 1 . 5. the value given is the differential input voltage. table 19: input delay measurement methodology (cont?d) description i /o standard attribute v l (1) v h (1) v meas (3)(5) v ref (2)(4) s e n d f e e d b a c k
artix-7 fpgas data sheet: dc and ac switching characteristics ds181 (v1.21) september 27, 2016 www.xilinx.com product specification 20 output delay measurements output delays are measured with short ou tput traces. standard termination was used for all testing. the propagation delay of the trace is characterized separately and subtracted from the final measurement, and is therefore not included in the generalized test setups shown in figure 1 and figure 2 . parameters v ref , r ref , c ref , and v meas fully describe the test conditions for each i/o standard. the most accurate prediction of propagation delay in any given application can be obtained through ibis simulation, using this method: 1. simulate the output driver of choice into the generalized test setup using values from table 20 . 2. record the time to v meas . 3. simulate the output driver of choice into the actual pcb trace and load using the appropriate ibis model or capacitance value to represent the load. 4. record the time to v meas . 5. compare the results of step 2 and step 4 . the increase or decrease in delay yiel ds the actual propagation delay of the pcb trace. x-ref target - figure 1 figure 1: single-ended test setup x-ref target - figure 2 figure 2: differential test setup table 20: output delay measurement methodology description i/o standard attribute r ref ( ) c ref (1) (pf) v meas (v) v ref (v) lvcmos, 1.2v lvcmos12 1m 0 0.6 0 lvcmos, 1.5v lvcmos15 1m 0 0.75 0 lvcmos, 1.8v lvcmos18 1m 0 0.9 0 lvcmos, 2.5v lvcmos25 1m 0 1.25 0 lvcmos, 3.3v lvcmos33 1m 0 1.65 0 lvttl, 3.3v lvttl 1m 0 1.65 0 pci33, 3.3v pci33_3 25 10 1.65 0 v ref r ref v mea s (volt a ge level when t a king del a y me asu rement) c ref (pro b e c a p a cit a nce) fpga o u tp u t d s 1 8 1_04_090514 r ref v mea s + ? c ref fpga o u tp u t d s 1 8 1_05_090514 s e n d f e e d b a c k
artix-7 fpgas data sheet: dc and ac switching characteristics ds181 (v1.21) september 27, 2016 www.xilinx.com product specification 21 hstl (high-speed transceiver logic), class i, 1.2v hstl_i_12 50 0 v ref 0.6 hstl, class i, 1.5v hstl_i 50 0 v ref 0.75 hstl, class ii, 1.5v hstl_ii 25 0 v ref 0.75 hstl, class i, 1.8v hstl_i_18 50 0 v ref 0.9 hstl, class ii, 1.8v hstl_ii_18 25 0 v ref 0.9 hsul (high-speed unterminated logic), 1.2v hsul_12 50 0 v ref 0.6 sstl12, 1.2v sstl12 50 0 v ref 0.6 sstl135/sstl135_r, 1.35v sstl135, sstl135_r 50 0 v ref 0.675 sstl15/sstl15_r, 1.5v sstl15, sstl15_r 50 0 v ref 0.75 sstl (stub series terminated logic), class i & class ii, 1.8v sstl18_i, sstl18_ii 50 0 v ref 0.9 diff_mobile_ddr, 1.8v diff_mobile_ddr 50 0 v ref 0.9 diff_hstl, class i, 1.2v diff_hstl_i_12 50 0 v ref 0.6 diff_hstl, class i & ii, 1.5v diff_hstl_i, diff_hstl_ii 50 0 v ref 0.75 diff_hstl, class i & ii, 1.8v diff _hstl_i_18, diff_hstl_ii_18 50 0 v ref 0.9 diff_hsul_12, 1.2v diff_hsul_12 50 0 v ref 0.6 diff_sstl135/diff_sst l135_r, 1.35v diff_sstl135, diff_sstl135_r 50 0 v ref 0.675 diff_sstl15/diff_ sstl15_r, 1.5v diff_sstl1 5, diff_sstl15_r 50 0 v ref 0.75 diff_sstl18, class i & ii, 1.8v di ff_sstl18_i, diff_sstl18_ii 50 0 v ref 0.9 lvds, 2.5v lvds_25 100 0 0 (2) 0 blvds (bus lvds), 2.5v blvds_25 100 0 0 (2) 0 mini lvds, 2.5v mini_lvds_25 100 0 0 (2) 0 ppds_25 ppds_25 100 0 0 (2) 0 rsds_25 rsds_25 100 0 0 (2) 0 tmds_33 tmds_33 50 0 0 (2) 3.3 notes: 1. c ref is the capacitance of the probe, nominally 0 pf. 2. the value given is the differential output voltage. table 20: output delay measurement methodology (cont?d) description i/o standard attribute r ref ( ) c ref (1) (pf) v meas (v) v ref (v) s e n d f e e d b a c k
artix-7 fpgas data sheet: dc and ac switching characteristics ds181 (v1.21) september 27, 2016 www.xilinx.com product specification 22 input/output logic switching characteristics table 21: ilogic switching characteristics symbol description speed grade units 1.0v 0.95v 0.9v -3 -2/-2le -1 -1q/-1m -1li -2le setup/hold t ice1ck / t ickce1 ce1 pin setup/hold with respect to clk 0.48/0.02 0.54/0.02 0. 76/0.02 0.76/0.02 0.76/0.02 0.50/?0.07 ns t isrck / t icksr sr pin setup/hold with respect to clk 0.60/0.01 0.70/0.01 1. 13/0.01 1.13/0.01 1.13/0.01 0.88/?0.35 ns t idock / t iockd d pin setup/hold with respect to clk without delay 0.01/0.27 0.01/0.29 0. 01/0.33 0.01/0.33 0.01/0.33 0.01/0.33 ns t idockd / t iockdd ddly pin setup/hold with respect to clk (using idelay) 0.02/0.27 0.02/0.29 0. 02/0.33 0.02/0.33 0.02/0.33 0.01/0.33 ns combinatorial t idi d pin to o pin propagation delay, no delay 0.11 0.11 0.13 0.13 0.13 0.14 ns t idid ddly pin to o pin propagation delay (using idelay) 0.11 0.12 0.14 0.14 0.14 0.15 ns sequential delays t idlo d pin to q1 pin using flip-flop as a latch without delay 0.41 0.44 0.51 0.51 0.51 0.54 ns t idlod ddly pin to q1 pin using flip-flop as a latch (using idelay) 0.41 0.44 0.51 0.51 0.51 0.55 ns t ickq clk to q outputs 0.53 0.57 0.66 0.66 0.66 0.71 ns t rq_ ilogic sr pin to oq/tq out 0.96 1.08 1.32 1.32 1.32 1.32 ns t gsrq_ ilogic global set/reset to q outputs 7.60 7.60 10.51 10.51 10.51 11.39 ns set/reset t rpw_ ilogic minimum pulse width, sr inputs 0.61 0.72 0.72 0.72 0.72 0.72 ns, min table 22: ologic switching characteristics symbol description speed grade units 1.0v 0.95v 0.9v -3 -2/-2le -1 -1q/-1m -1li -2le setup/hold t odck / t ockd d1/d2 pins setup/hold with respect to clk 0.67/?0.11 0.71/?0.11 0.84/?0.11 0.84/?0.06 0. 84/?0.11 0.64/0.03 ns t ooceck / t ockoce oce pin setup/hold with respect to clk 0.32/0.58 0.34/0.58 0.51/0.58 0 .51/0.58 0.51/0.58 0.28/0.01 ns t osrck / t ocksr sr pin setup/hold with respect to clk 0.37/0.21 0.44/0.21 0.80/0.21 0 .80/0.21 0.80/0. 21 0.62/?0.25 ns t otck / t ockt t1/t2 pins setup/hold with respect to clk 0.69/?0.14 0.73/?0.14 0.89/?0.14 0.89/?0.11 0. 89/?0.14 0.66/0.02 ns t otceck / t ocktce tce pin setup/hold with respect to clk 0.32/0.01 0.34/0.01 0.51/0.01 0 .51/0.10 0.51/0.01 0.24/0.05 ns s e n d f e e d b a c k
artix-7 fpgas data sheet: dc and ac switching characteristics ds181 (v1.21) september 27, 2016 www.xilinx.com product specification 23 input serializer/deserializer switching characteristics combinatorial t odq d1 to oq out or t1 to tq out 0.83 0.96 1.16 1.16 1.16 1.36 ns sequential delays t ockq clk to oq/tq out 0.47 0. 49 0.56 0.56 0.56 0.63 ns t rq_ologic sr pin to oq/tq out 0.72 0.80 0.95 0.95 0.95 1.12 ns t gsrq_ologic global set/reset to q outputs 7.60 7.60 10.51 10.51 10.51 11.39 ns set/reset t rpw_ologic minimum pulse width, sr inputs 0 .64 0.74 0.74 0.74 0.74 0.74 ns, min table 23: iserdes switching characteristics symbol description speed grade units 1.0v 0.95v 0.9v -3 -2/-2le -1 -1q/-1m -1li -2le setup/hold for control lines t iscck_bitslip / t isckc_bitslip bitslip pin setup/hold with respect to clkdiv 0.01/0.14 0.02/0.15 0 .02/0.17 0.02/0.17 0. 02/0.17 0.02/0.21 ns t iscck_ce / t isckc_ce (2) ce pin setup/hold with respect to clk (for ce1) 0.45/?0.01 0.50/?0.01 0.72/?0.01 0. 72/?0.01 0.72/?0.01 0.45/?0.11 ns t iscck_ce2 / t isckc_ce2 (2) ce pin setup/hold with respect to clkdiv (for ce2) ?0.10/0.33 ?0.10/0.36 ?0.10/0.40 ?0 .10/0.40 ?0.10/0.40 ?0.17/0.40 ns setup/hold fo r data lines t isdck_d / t isckd_d d pin setup/hold with respect to clk ?0.02/0.12 ?0.02/0.14 ?0.02/0.17 ?0 .02/0.17 ?0.02/0.17 ?0.04/0.19 ns t isdck_ddly / t isckd_ddly ddly pin setup/hold with respect to clk (using idelay) (1) ?0.02/0.12 ?0.02/0.14 ?0.02/0.17 ?0 .02/0.17 ?0.02/0.17 ?0.03/0.19 ns t isdck_d_ddr / t isckd_d_ddr d pin setup/hold with respect to clk at ddr mode ?0.02/0.12 ?0.02/0.14 ?0.02/0.17 ?0 .02/0.17 ?0.02/0.17 ?0.04/0.19 ns t isdck_ddly_ddr / t isckd_ddly_ddr d pin setup/hold with respect to clk at ddr mode (using idelay) (1) 0.12/0.12 0.14/0.14 0 .17/0.17 0.17/0.17 0. 17/0.17 0.19/0.19 ns sequential delays t iscko_q clkdiv to out at q pin 0.53 0.54 0.66 0.66 0.66 0.67 ns propagation delays t isdo_do d input to do output pin 0.11 0.11 0.13 0.13 0.13 0.14 ns notes: 1. recorded at 0 tap value. 2. t iscck_ce2 and t isckc_ce2 are reported as t iscck_ce /t isckc_ce in the timing report. table 22: ologic switching characteristics (cont?d) symbol description speed grade units 1.0v 0.95v 0.9v -3 -2/-2le -1 -1q/-1m -1li -2le s e n d f e e d b a c k
artix-7 fpgas data sheet: dc and ac switching characteristics ds181 (v1.21) september 27, 2016 www.xilinx.com product specification 24 output serializer/deserializer switching characteristics table 24: oserdes switching characteristics symbol description speed grade units 1.0v 0.95v 0.9v -3 -2/-2le -1 -1q/-1m -1li -2le setup/hold t osdck_d / t osckd_d d input setup/hold with respect to clkdiv 0.42/0.03 0.45/0.03 0. 63/0.03 0.63/0.08 0.63 /0.03 0.44/?0.02 ns t osdck_t / t osckd_t (1) t input setup/hold with respect to clk 0.69/?0.13 0.73/?0.13 0.88/?0.13 0 .88/?0.13 0.88/?0.13 0.66/?0.25 ns t osdck_t2 / t osckd_t2 (1) t input setup/hold with respect to clkdiv 0.31/?0.13 0.34/?0.13 0.39/?0.13 0 .39/?0.13 0.39/?0.13 0.46/?0.25 ns t oscck_oce / t osckc_oce oce input setup/hold with respect to clk 0.32/0.58 0.34/0.58 0. 51/0.58 0.51/0.58 0.51 /0.58 0.28/?0.04 ns t oscck_s sr (reset) input setup with respect to clkdiv 0.47 0.52 0.85 0.85 0.85 0.70 ns t oscck_tce / t osckc_tce tce input setup/hold with respect to clk 0.32/0.01 0.34/0.01 0. 51/0.01 0.51/0.10 0.51 /0.01 0.24/0.00 ns sequential delays t oscko_oq clock to out from clk to oq 0.40 0.42 0.48 0.48 0.48 0.54 ns t oscko_tq clock to out from clk to tq 0.47 0.49 0.56 0.56 0.56 0.63 ns combinatorial t osdo_ttq t input to tq out 0.83 0.92 1.11 1.11 1.11 1.18 ns notes: 1. t osdck_t2 and t osckd_t2 are reported as t osdck_t /t osckd_t in the timing report. s e n d f e e d b a c k
artix-7 fpgas data sheet: dc and ac switching characteristics ds181 (v1.21) september 27, 2016 www.xilinx.com product specification 25 input/output delay switching characteristics table 25: input/output delay switching characteristics symbol description speed grade units 1.0v 0.95v 0.9v -3 -2/-2le -1 -1q/-1m -1li -2le idelayctrl t dlycco_rdy reset to ready for idelayctrl 3.67 3.67 3.67 3.67 3.67 3.67 s f idelayctrl_ref attribute refclk frequency = 200.00 (1) 200.00 200.00 200.00 200.00 200.00 200.00 mhz attribute refclk frequency = 300.00 (1) 300.00 300.00 300.00 300.00 300.00 300.00 mhz attribute refclk frequency = 400.00 (1) 400.00 400.00 n/a n/a n/a n/a mhz idelayctrl_ref_ precision refclk precision 10 10 10 10 10 10 mhz t idelayctrl_rpw minimum reset pulse width 59.28 59.28 59.28 59.28 59.28 59.28 ns idelay t idelayresolution idelay chain delay resolution 1/(32 x 2 x f ref )ps t idelaypat_jit pattern dependent period jitter in delay chain for clock pattern. (2) 000000ps per tap pattern dependent period jitter in delay chain for random data pattern (prbs 23) (3) 5 5 5 5 5 5 ps per tap pattern dependent period jitter in delay chain for random data pattern (prbs 23) (4) 9 9 9 9 9 9 ps per tap t idelay_clk_max maximum frequency of clk input to idelay 680.00 680.00 600.00 600.00 600.00 520.00 mhz t idcck_ce / t idckc_ce ce pin setup/hold with respect to c for idelay 0.12/0.11 0.16/0.13 0 .21/0.16 0.21/0.16 0. 21/0.16 0.14/0.16 ns t idcck_inc / t idckc_inc inc pin setup/hold with respect to c for idelay 0.12/0.16 0.14/0.18 0 .16/0.22 0.16/0.23 0. 16/0.22 0.10/0.23 ns t idcck_rst / t idckc_rst rst pin setup/hold with respect to c for idelay 0.15/0.09 0.16/0.11 0 .18/0.14 0.18/0.14 0. 18/0.14 0.22/0.19 ns t iddo_idatain propagation delay through idelay note 5 note 5 note 5 note 5 note 5 note 5 ps notes: 1. average tap delay at 200 mhz = 78 ps, at 300 mhz = 52 ps, and at 400 mhz = 39 ps. 2. when high_performance mode is set to true or false. 3. when high_performance mode is set to true. 4. when high_performance mode is set to false. 5. delay depends on idelay tap setting. see the timing report for actual values. s e n d f e e d b a c k
artix-7 fpgas data sheet: dc and ac switching characteristics ds181 (v1.21) september 27, 2016 www.xilinx.com product specification 26 table 26: io_fifo switching characteristics symbol description speed grade units 1.0v 0.95v 0.9v -3 -2/-2le -1 -1q/-1m -1li -2le io_fifo clock to out delays t offcko_do rdclk to q outputs 0.55 0.60 0.68 0.68 0.68 0.81 ns t cko_flags clock to io_fifo flags 0. 55 0.61 0.77 0.77 0.77 0.79 ns setup/hold t cck_d /t ckc_d d inputs to wrclk 0.47/ 0.02 0.51/0.02 0.58/0.02 0.5 8/0.18 0.58/0.02 0.76/0.09 ns t iffcck_wren / t iffckc_wren wren to wrclk 0.42/?0.01 0.47/?0.01 0. 53/?0.01 0.53/?0.01 0.53 /?0.01 0.70/?0.05 ns t offcck_rden / t offckc_rden rden to rdclk 0.53/0.02 0. 58/0.02 0.66/0.02 0.66/0. 02 0.66/0.02 0.79/?0.02 ns minimum pulse width t pwh_io_fifo reset, rdclk, wrclk 1.62 2.15 2.15 2.15 2.15 2.15 ns t pwl_io_fifo reset, rdclk, wrclk 1.62 2.15 2.15 2.15 2.15 2.15 ns maximum frequency f max rdclk and wrclk 266.67 200.00 200.00 200.00 200.00 200.00 mhz s e n d f e e d b a c k
artix-7 fpgas data sheet: dc and ac switching characteristics ds181 (v1.21) september 27, 2016 www.xilinx.com product specification 27 clb switching characteristics table 27: clb switching ch aracteristics symbol description speed grade units 1.0v 0.95v 0.9v -3 -2/-2le -1 -1q/-1m -1li -2le combinatorial delays t ilo an ? dn lut address to a 0.10 0.11 0.13 0.13 0.13 0.15 ns, max t ilo_2 an ? dn lut address to amux/cmux 0.27 0.30 0.36 0.36 0.36 0.41 ns, max t ilo_3 an ? dn lut address to bmux_a 0.42 0.46 0.55 0.55 0.55 0.65 ns, max t ito an ? dn inputs to a ? d q outputs 0.94 1.05 1.27 1.27 1.27 1.51 ns, max t axa ax inputs to amux output 0.62 0.69 0.84 0.84 0.84 1.01 ns, max t axb ax inputs to bmux output 0.58 0.66 0.83 0.83 0.83 0.98 ns, max t axc ax inputs to cmux output 0.60 0.68 0.82 0.82 0.82 0.98 ns, max t axd ax inputs to dmux output 0.68 0.75 0.90 0.90 0.90 1.08 ns, max t bxb bx inputs to bmux output 0.51 0.57 0.69 0.69 0.69 0.82 ns, max t bxd bx inputs to dmux output 0.62 0.69 0.82 0.82 0.82 0.99 ns, max t cxc cx inputs to cmux output 0.42 0.48 0.58 0.58 0.58 0.69 ns, max t cxd cx inputs to dmux output 0.53 0.59 0.71 0.71 0.71 0.86 ns, max t dxd dx inputs to dmux output 0.52 0.58 0.70 0.70 0.70 0.84 ns, max sequential delays t cko clock to aq ? dq outputs 0.40 0.44 0.53 0.53 0.53 0.62 ns, max t shcko clock to amux ? dmux outputs 0.47 0.53 0.66 0.66 0.66 0.73 ns, max setup and hold times of clb fl ip-flops before/after clock clk t as /t ah a n ? d n input to clk on a ? d flip-flops 0.07/0.12 0.09/0.14 0.11/ 0.18 0.11/0. 28 0.11/0.18 0.11/0.22 ns, min t dick / t ckdi a x ?d x input to clk on a ? d flip-flops 0.06/0.19 0.07/0.21 0.09/ 0.26 0.09/0. 35 0.09/0.26 0.09/0.33 ns, min a x ?d x input through muxs and/or carry logic to clk on a ? d flip-flops 0.59/0.08 0.66/0.09 0.81/ 0.11 0.81/0. 20 0.81/0.11 0.97/0.15 ns, min t ceck_clb / t ckce_clb ce input to clk on a ? d flip-flops 0.15 /0.00 0.17/0.00 0.21/0. 01 0.21/0.13 0.21/0.01 0.34/?0.01 ns, min t srck / t cksr sr input to clk on a ? d flip-flops 0.38 /0.03 0.43/0.04 0.53/0. 05 0.53/0.18 0.53/0.05 0.62/0.19 ns, min set/reset t srmin sr input minimum pulse width 0.52 0.78 1.04 1.04 1.04 0.95 ns, min t rq delay from sr input to aq ? dq flip-flops 0.53 0.59 0.71 0.71 0.71 0.83 ns, max t ceo delay from ce input to aq ? dq flip-flops 0.52 0.58 0.70 0.70 0.70 0.83 ns, max f tog toggle frequency (for export control) 1412 1286 1098 1098 1098 1098 mhz s e n d f e e d b a c k
artix-7 fpgas data sheet: dc and ac switching characteristics ds181 (v1.21) september 27, 2016 www.xilinx.com product specification 28 clb distributed ram switching characteristics (slicem only) clb shift register switching characteristics (slicem only) table 28: clb distributed ram swit ching characteristics symbol description speed grade units 1.0v 0.95v 0.9v -3 -2/-2le -1 -1q/-1m -1li -2le sequential delays t shcko clock to a ? b outputs 0.98 1.09 1.32 1.32 1.32 1.54 ns, max t shcko_1 clock to amux ? bmux outputs 1.37 1.53 1.86 1.86 1.86 2.18 ns, max setup and hold times before/after clock clk t ds_lram / t dh_lram a ? d inputs to clk 0.54/0.28 0.60/0.30 0.72 /0.35 0.72/0.37 0.72/0. 35 0.96/0.40 ns, min t as_lram / t ah_lram address an inputs to clock 0 .27/0.55 0.30/0.60 0.37/0.70 0.37/ 0.71 0.37/0.70 0. 43/0.71 ns, min address an inputs through muxs and/or carry logic to clock 0.69/0.18 0.77/0.21 0.94/0.26 0.94/ 0.35 0.94/0.26 1. 11/0.31 ns, min t ws_lram / t wh_lram we input to clock 0.38/0. 10 0.43/0.12 0.53/0.17 0.53/0. 17 0.53/0.17 0.62/ 0.13 ns, min t ceck_lram / t ckce_lram ce input to clk 0.39/0.10 0.44/0.11 0.53/0.17 0.53/0.17 0.53/0.17 0.63/ 0.12 ns, min clock clk t mpw_lram minimum pulse width 1.05 1.1 31.251.251.251.61ns, min t mcp minimum clock period 2.10 2.26 2.50 2.50 2.50 3.21 ns, min notes: 1. t shcko also represents the clk to xmux output. refer to the timing report for the clk to xmux path. table 29: clb shift register switching characteristics symbol description speed grade units 1.0v 0.95v 0.9v -3 -2/-2le -1 -1q/-1m -1li -2le sequential delays t reg clock to a ? d outputs 1.19 1.33 1.61 1.61 1.61 1.89 ns, max t reg_mux clock to amux ? dmux output 1.58 1.77 2.15 2.15 2.15 2.53 ns, max t reg_m31 clock to dmux output via m31 output 1.12 1.23 1.46 1.46 1.46 1.68 ns, max setup and hold times before/after clock clk t ws_shfreg / t wh_shfreg we input 0.37/0.10 0.41/0.12 0.51/ 0.17 0.51/0.17 0.51/0.17 0.59/0.13 ns, min t ceck_shfreg / t ckce_shfreg ce input to clk 0.37/0.10 0.42/0.11 0.52/ 0.17 0.52/0.17 0.52/0.17 0.60/0.12 ns, min t ds_shfreg / t dh_shfreg a ? d inputs to clk 0.33/0.34 0.37/0.37 0.44/ 0.43 0.44/0.44 0.44/0.43 0.54/0.55 ns, min clock clk t mpw_shfreg minimum pulse width 0.77 0.86 0.98 0.98 0.98 1.22 ns, min s e n d f e e d b a c k
artix-7 fpgas data sheet: dc and ac switching characteristics ds181 (v1.21) september 27, 2016 www.xilinx.com product specification 29 block ram and fifo switching characteristics table 30: block ram and fifo switching characteristics symbol description speed grade units 1.0v 0.95v 0.9v -3 -2/-2le -1 -1q/-1m -1li -2le block ram and fifo clock-to-out delays t rcko_do and t rcko_do_reg (1) clock clk to dout output (without output register) (2)(3) 1.85 2.13 2.46 2.46 2.46 2.87 ns, max clock clk to dout output (with output register) (4)(5) 0.64 0.74 0.89 0.89 0.89 1.02 ns, max t rcko_do_ecc and t rcko_do_ecc_reg clock clk to dout output with ecc (without output register) (2)(3) 2.77 3.04 3.84 3.84 3.84 5.30 ns, max clock clk to dout output with ecc (with output register) (4)(5) 0.73 0.81 0.94 0.94 0.94 1.11 ns, max t rcko_do_cascout and t rcko_do_cascout_reg clock clk to dout output with cascade (without output register) (2) 2.61 2.88 3.30 3.30 3.30 3.76 ns, max clock clk to dout output with cascade (with output register) (4) 1.16 1.28 1.46 1.46 1.46 1.56 ns, max t rcko_flags clock clk to fifo flags outputs (6) 0.76 0.87 1.05 1.05 1.05 1.14 ns, max t rcko_pointers clock clk to fifo pointers outputs (7) 0.94 1.02 1.15 1.15 1.15 1.30 ns, max t rcko_parity_ecc clock clk to eccparity in ecc encode only mode 0.78 0.85 0.94 0.94 0.94 1.10 ns, max t rcko_sdbit_ecc and t rcko_sdbit_ecc_reg clock clk to biterr (without output register) 2.56 2.81 3.55 3.55 3.55 4.90 ns, max clock clk to biterr (with output register) 0.68 0.76 0.89 0.89 0.89 1.05 ns, max t rcko_rdaddr_ecc and t rcko_rdaddr_ecc_reg clock clk to rdaddr output with ecc (without output register) 0.75 0.88 1.07 1.07 1.07 1.15 ns, max clock clk to rdaddr output with ecc (with output register) 0.84 0.93 1.08 1.08 1.08 1.29 ns, max setup and hold times before/after clock clk t rcck_addra / t rckc_addra addr inputs (8) 0.45/0.31 0.49/0.33 0.57 /0.36 0.57/0.52 0.57/0.36 0.77/0.45 ns, min t rdck_di_wf_nc / t rckd_di_wf_nc data input setup/hold time when block ram is configured in write_first or no_change mode (9) 0.58/0.60 0.65/0.63 0.74 /0.67 0.74/0.67 0.74/0.67 0.92/0.76 ns, min t rdck_di_rf / t rckd_di_rf data input setup/hold time when block ram is configured in read_first mode (9) 0.20/0.29 0.22/0.34 0.25 /0.41 0.25/0.50 0.25/0.41 0.29/0.38 ns, min s e n d f e e d b a c k
artix-7 fpgas data sheet: dc and ac switching characteristics ds181 (v1.21) september 27, 2016 www.xilinx.com product specification 30 t rdck_di_ecc / t rckd_di_ecc din inputs with block ram ecc in standard mode (9) 0.50/0.43 0.55/0.46 0.63 /0.50 0.63/0.50 0.63/0.50 0.78/0.54 ns, min t rdck_di_eccw / t rckd_di_eccw din inputs with block ram ecc encode only (9) 0.93/0.43 1.02/0.46 1.17 /0.50 1.17/0.50 1.17/0.50 1.38/0.48 ns, min t rdck_di_ecc_fifo / t rckd_di_ecc_fifo din inputs with fifo ecc in standard mode (9) 1.04/0.56 1.15/0.59 1.32 /0.64 1.32/0.64 1.32/0.64 1.55/0.77 ns, min t rcck_injectbiterr / t rckc_injectbiterr inject single/double bit error in ecc mode 0.58/0.35 0.64/0.37 0.74 /0.40 0.74/0.52 0.74/0.40 0.92/0.48 ns, min t rcck_en /t rckc_en block ram enable (en) input 0.35/0.20 0.39/0.21 0.45 /0.23 0.45/0.41 0.45/0.23 0.57/0.26 ns, min t rcck_regce / t rckc_regce ce input of output register 0.24/0.15 0.29/0.15 0.36 /0.16 0.36/0.39 0.36/0.16 0.40/0.19 ns, min t rcck_rstreg / t rckc_rstreg synchronous rstreg input 0.29/0.07 0.32/0.07 0.35 /0.07 0.35/0.17 0.35/0.07 0.41/0.07 ns, min t rcck_rstram / t rckc_rstram synchronous rstram input 0.32/0.42 0.34/0.43 0.36 /0.46 0.36/0.57 0.36/0.46 0.40/0.47 ns, min t rcck_wea / t rckc_wea write enable (we) input (block ram only) 0.44/0.18 0.48/0.19 0.54 /0.20 0.54/0.42 0.54/0.20 0.64/0.23 ns, min t rcck_wren / t rckc_wren wren fifo inputs 0.46/0.30 0.46/0.35 0.47/0.43 0.47/0.43 0.47/0.43 0.77/0.44 ns, min t rcck_rden / t rckc_rden rden fifo inputs 0.42/0.30 0.43/0.35 0.43/0.43 0.43/0.62 0.43/0.43 0.71/0.50 ns, min reset delays t rco_flags reset rst to fifo flags/pointers (10) 0.90 0.98 1.10 1.10 1.10 1.25 ns, max t rrec_rst / t rrem_rst fifo reset recovery and removal timing (11) 1.87/?0.81 2.07/?0.81 2. 37/?0.81 2.37/?0.58 2.37/ ?0.81 2.44/?0.71 ns, max maximum frequency f max_bram_wf_nc block ram (write first and no change modes) when not in sdp rf mode 509.68 460.83 388.20 388.20 388.20 315.66 mhz f max_bram_rf_ performance block ram (read first, performance mode) when in sdp rf mode but no address overlap between port a and port b 509.68 460.83 388.20 388.20 388.20 315.66 mhz f max_bram_rf_ delayed_write block ram (read first, delayed write mode) when in sdp rf mode and there is possibility of overlap between port a and port b addresses 447.63 404.53 339.67 339.67 339.67 268.96 mhz table 30: block ram and fifo switching characteristics (cont?d) symbol description speed grade units 1.0v 0.95v 0.9v -3 -2/-2le -1 -1q/-1m -1li -2le s e n d f e e d b a c k
artix-7 fpgas data sheet: dc and ac switching characteristics ds181 (v1.21) september 27, 2016 www.xilinx.com product specification 31 f max_cas_wf_nc block ram cascade (write first, no change mode) when cascade but not in rf mode 467.07 418.59 345.78 345.78 345.78 273.30 mhz f max_cas_rf_ performance block ram cascade (read first, performance mode) when in cascade with rf mode and no possibility of address overlap/one port is disabled 467.07 418.59 345.78 345.78 345.78 273.30 mhz f max_cas_rf_ delayed_write when in cascade rf mode and there is a possibility of address overlap between port a and port b 405.35 362.19 297.35 297.35 297.35 226.60 mhz f max_fifo fifo in all modes without ecc 509.68 460.83 388.20 388.20 388.20 315.66 mhz f max_ecc block ram and fifo in ecc configuration 410.34 365.10 297.53 297.53 297.53 215.38 mhz notes: 1. the timing report shows all of these parameters as t rcko_do . 2. t rcko_dor includes t rcko_dow , t rcko_dopr , and t rcko_dopw as well as the b port equivalent timing parameters. 3. these parameters also apply to synchronous fifo with do_reg = 0. 4. t rcko_do includes t rcko_dop as well as the b port equivalent timing parameters. 5. these parameters also apply to multirate (asynchronous) and synchronous fifo with do_reg = 1. 6. t rcko_flags includes the following parameters: t rcko_aempty , t rcko_afull , t rcko_empty , t rcko_full , t rcko_rderr , t rcko_wrerr. 7. t rcko_pointers includes both t rcko_rdcount and t rcko_wrcount. 8. the addr setup and hold must be met when en is asserted (even when we is deasserted) . otherwise, block ram data corruption is possible. 9. these parameters include both a and b inputs as well as the parity inputs of a and b. 10. t rco_flags includes the following flags: aempty, afull, em pty, full, rderr, wrer r, rdcount, and wrcount. 11. rden and wren must be held low prior to and during reset. the fifo reset must be asserted for at least five positive clock e dges of the slowest clock (wrclk or rdclk). table 30: block ram and fifo switching characteristics (cont?d) symbol description speed grade units 1.0v 0.95v 0.9v -3 -2/-2le -1 -1q/-1m -1li -2le s e n d f e e d b a c k
artix-7 fpgas data sheet: dc and ac switching characteristics ds181 (v1.21) september 27, 2016 www.xilinx.com product specification 32 dsp48e1 switching characteristics table 31: dsp48e1 switching characteristics symbol description speed grade units 1.0v 0.95v 0.9v -3 -2/-2le -1 -1q/-1m -1li -2le setup and hold times of data/control pins to the input register clock t dspdck_a_areg / t dspckd_a_areg a input to a register clk 0.26/ 0.12 0.30/ 0.13 0.37/ 0.14 0.37/ 0.28 0.37/ 0.14 0.45/ 0.14 ns t dspdck_b_breg / t dspckd_b_breg b input to b register clk 0.33/ 0.15 0.38/ 0.16 0.45/ 0.18 0.45/ 0.25 0.45/ 0.18 0.60/ 0.19 ns t dspdck_c_creg / t dspckd_c_creg c input to c register clk 0.17/ 0.17 0.20/ 0.19 0.24/ 0.21 0.24/ 0.26 0.24/ 0.21 0.34/ 0.29 ns t dspdck_d_dreg / t dspckd_d_dreg d input to d register clk 0.25/ 0.25 0.32/ 0.27 0.42/ 0.27 0.42/ 0.42 0.42/ 0.27 0.54/ 0.23 ns t dspdck_acin_areg / t dspckd_acin_areg acin input to a register clk 0.23/ 0.12 0.27/ 0.13 0.32/ 0.14 0.32/ 0.17 0.32/ 0.14 0.36/ 0.14 ns t dspdck_bcin_breg / t dspckd_bcin_breg bcin input to b register clk 0.25/ 0.15 0.29/ 0.16 0.36/ 0.18 0.36/ 0.18 0.36/ 0.18 0.41/ 0.19 ns setup and hold times of data pins to the pipeline register clock t dspdck_ { a, b } _mreg_mult / t dspckd_{a, b}_mreg_mult {a, b} input to m register clk using multiplier 2.40/ ?0.01 2.76/ ?0.01 3.29/ ?0.01 3.29/ ?0.01 3.29/ ?0.01 4.31/ ?0.07 ns t dspdck_ { a, d } _adreg / t dspckd_{a, d}_adreg {a, d} input to ad register clk 1.29/ ?0.02 1.48/ ?0.02 1.76/ ?0.02 1.76/ ?0.02 1.76/ ?0.02 2.29/ ?0.27 ns setup and hold times of data/control pins to the output register clock t dspdck_{a, b}_preg_mult / t dspckd_{a, b} _preg_mult {a, b} input to p register clk using multiplier 4.02/ ?0.28 4.60/ ?0.28 5.48/ ?0.28 5.48/ ?0.28 5.48/ ?0.28 6.95/ ?0.48 ns t dspdck_d_preg_mult / t dspckd_d_preg_mult d input to p register clk using multiplier 3.93/ ?0.73 4.50/ ?0.73 5.35/ ?0.73 5.35/ ?0.73 5.35/ ?0.73 6.73/ ?1.68 ns t dspdck_{a, b} _preg / t dspckd_{a, b} _preg a or b input to p register clk not using multiplier 1.73/ ?0.28 1.98/ ?0.28 2.35/ ?0.28 2.35/ ?0.28 2.35/ ?0.28 2.80/ ?0.48 ns t dspdck_c_preg / t dspckd_c_preg c input to p register clk not using multiplier 1.54/ ?0.26 1.76/ ?0.26 2.10/ ?0.26 2.10/ ?0.26 2.10/ ?0.26 2.54/ ?0.45 ns t dspdck_pcin_preg / t dspckd_pcin_preg pcin input to p register clk 1.32/ ?0.15 1.51/ ?0.15 1.80/ ?0.15 1.80/ ?0.15 1.80/ ?0.15 2.13/ ?0.25 ns setup and hold times of the ce pins t dspdck_{cea;ceb}_{areg;breg} / t dspckd_{cea;ceb}_{areg;breg} {cea; ceb} input to {a; b} register clk 0.35/ 0.06 0.42/ 0.08 0.52/ 0.11 0.52/ 0.11 0.52/ 0.11 0.64/ 0.11 ns t dspdck_cec_creg / t dspckd_cec_creg cec input to c register clk 0.28/ 0.10 0.34/ 0.11 0.42/ 0.13 0.42/ 0.13 0.42/ 0.13 0.49/ 0.16 ns t dspdck_ced_dreg / t dspckd_ced_dreg ced input to d register clk 0.36/ ?0.03 0.43/ ?0.03 0.52/ ?0.03 0.52/ ?0.03 0.52/ ?0.03 0.68/ 0.14 ns t dspdck_cem_mreg / t dspckd_cem_mreg cem input to m register clk 0.17/ 0.18 0.21/ 0.20 0.27/ 0.23 0.27/ 0.23 0.27/ 0.23 0.45/ 0.29 ns t dspdck_cep_preg / t dspckd_cep_preg cep input to p register clk 0.36/ 0.01 0.43/ 0.01 0.53/ 0.01 0.53/ 0.01 0.53/ 0.01 0.63/ 0.00 ns s e n d f e e d b a c k
artix-7 fpgas data sheet: dc and ac switching characteristics ds181 (v1.21) september 27, 2016 www.xilinx.com product specification 33 setup and hold times of the rst pins t dspdck_{rsta; rstb}_{areg; breg} / t dspckd_{rsta; rstb}_{areg; breg} {rsta, rstb} input to {a, b} register clk 0.41/ 0.11 0.46/ 0.13 0.55/ 0.15 0.55/ 0.24 0.55/ 0.15 0.63/ 0.40 ns t dspdck_rstc_creg / t dspckd_rstc_creg rstc input to c register clk 0.07/ 0.10 0.08/ 0.11 0.09/ 0.12 0.09/ 0.25 0.09/ 0.12 0.13/ 0.11 ns t dspdck_rstd_dreg / t dspckd_rstd_dreg rstd input to d register clk 0.44/ 0.07 0.50/ 0.08 0.59/ 0.09 0.59/ 0.09 0.59/ 0.09 0.67/ 0.08 ns t dspdck_rstm_mreg / t dspckd_rstm_mreg rstm input to m register clk 0.21/ 0.22 0.23/ 0.24 0.27/ 0.28 0.27/ 0.28 0.27/ 0.28 0.28/ 0.35 ns t dspdck_rstp_preg / t dspckd_rstp_preg rstp input to p register clk 0.27/ 0.01 0.30/ 0.01 0.35/ 0.01 0.35/ 0.03 0.35/ 0.01 0.43/ 0.00 ns combinatorial delays from input pins to output pins t dspdo_a_carryout_mult a input to carryout output using multiplier 3.79 4.35 5.18 5.18 5.18 6.61 ns t dspdo_d_p_mult d input to p output using multiplier 3.72 4.26 5.07 5.07 5.07 6.41 ns t dspdo_b_p b input to p output not using multiplier 1.53 1.75 2.08 2.08 2.08 2.48 ns t dspdo_c_p c input to p output 1.33 1.53 1.82 1.82 1.82 2.22 ns combinatorial delays from input pins to cascading output pins t dspdo_{a; b}_{acout; bcout} {a, b} input to {acout, bcout} output 0.55 0.63 0.74 0.74 0.74 0.87 ns t dspdo_{a, b}_carrycascout_mult {a, b} input to carrycascout output using multiplier 4.06 4.65 5.54 5.54 5.54 7.03 ns t dspdo_d_carr ycascout_mult d input to carrycascout output using multiplier 3.97 4.54 5.40 5.40 5.40 6.81 ns t dspdo_{a, b}_carrycascout {a, b} input to carrycascout output not using multiplier 1.77 2.03 2.41 2.41 2.41 2.88 ns t dspdo_c_carrycascout c input to carrycascout output 1.58 1.81 2.15 2.15 2.15 2.62 ns combinatorial delays from cascading input pins to all output pins t dspdo_acin_p_mult acin input to p output using multiplier 3.65 4.19 5.00 5.00 5.00 6.40 ns t dspdo_acin_p acin input to p output not using multiplier 1.37 1.57 1.88 1.88 1.88 2.44 ns t dspdo_acin_acout acin input to acout output 0.38 0.44 0.53 0.53 0.53 0.63 ns t dspdo_acin_car rycascout_mult acin input to carrycascout output using multiplier 3.90 4.47 5.33 5.33 5.33 6.79 ns t dspdo_acin_carrycascout acin input to carrycascout output not using multiplier 1.61 1.85 2.21 2.21 2.21 2.84 ns t dspdo_pcin_p pcin input to p output 1. 11 1.28 1.52 1.52 1.52 1.82 ns t dspdo_pcin_carrycascout pcin input to carrycascout output 1.36 1.56 1.85 1.85 1.85 2.21 ns table 31: dsp48e1 switching characteristics (cont?d) symbol description speed grade units 1.0v 0.95v 0.9v -3 -2/-2le -1 -1q/-1m -1li -2le s e n d f e e d b a c k
artix-7 fpgas data sheet: dc and ac switching characteristics ds181 (v1.21) september 27, 2016 www.xilinx.com product specification 34 clock to outs from output re gister clock to output pins t dspcko_p_preg clk preg to p output 0.33 0.37 0.44 0.44 0.44 0.54 ns t dspcko_carrycascout_preg clk preg to carrycascout output 0.52 0.59 0.69 0.69 0.69 0.84 ns clock to outs from pipeline register clock to output pins t dspcko_p_mreg clk mreg to p output 1.68 1.93 2.31 2.31 2.31 2.73 ns t dspcko_carrycascout_mreg clk mreg to carrycascout output 1.92 2.21 2.64 2.64 2.64 3.12 ns t dspcko_p_adreg_mult clk adreg to p output using multiplier 2.72 3.10 3.69 3.69 3.69 4.60 ns t dspcko_carrycascout_adreg_ mult clk adreg to carrycascout output using multiplier 2.96 3.38 4.02 4.02 4.02 4.99 ns clock to outs from input re gister clock to output pins t dspcko_p_areg_mult clk areg to p output using multiplier 3.94 4.51 5.37 5.37 5.37 6.84 ns t dspcko_p_breg clk breg to p output not using multiplier 1.64 1.87 2.22 2.22 2.22 2.65 ns t dspcko_p_creg clk creg to p output not using multiplier 1.69 1.93 2.30 2.30 2.30 2.81 ns t dspcko_p_dreg_mult clk dreg to p output using multiplier 3.91 4.48 5.32 5.32 5.32 6.77 ns clock to outs from input register clock to cascadi ng output pins t dspcko_{acout; bcout}_{areg; breg} clk (acout, bcout) to {a,b} register output 0.64 0.73 0.87 0.87 0.87 1.02 ns t dspcko_carrycascout_{areg, breg}_mult clk (areg, breg) to carrycascout output using multiplier 4.19 4.79 5.70 5.70 5.70 7.24 ns t dspcko_carrycascout_ breg clk breg to carrycascout output not using multiplier 1.88 2.15 2.55 2.55 2.55 3.04 ns t dspcko_carrycascout_ dreg_mult clk dreg to carrycascout output using multiplier 4.16 4.76 5.65 5.65 5.65 7.17 ns t dspcko_carrycascout_ creg clk creg to carrycascout output 1.94 2.21 2.63 2.63 2.63 3.20 ns maximum frequency f max with all registers used 628.93 550.66 464.25 464.25 464.25 363.77 mhz f max_patdet with pattern detector 531.63 465.77 392.93 392.93 392.93 310.08 mhz f max_mult_nomreg two register multiply without mreg 349.28 305.62 257.47 257.47 257.47 210.44 mhz f max_mult_nomreg_patdet two register multiply without mreg with pattern detect 317.26 277.62 233.92 233.92 233.92 191.28 mhz f max_preadd_mult_noadreg without adreg 397.30 346.26 290.44 290.44 290.44 223.26 mhz f max_preadd_mult_noadreg_ patdet without adreg with pattern detect 397.30 346.26 290.44 290.44 290.44 223.26 mhz table 31: dsp48e1 switching characteristics (cont?d) symbol description speed grade units 1.0v 0.95v 0.9v -3 -2/-2le -1 -1q/-1m -1li -2le s e n d f e e d b a c k
artix-7 fpgas data sheet: dc and ac switching characteristics ds181 (v1.21) september 27, 2016 www.xilinx.com product specification 35 clock buffers and networks f max_nopipelinereg without pipeline registers (mreg, adreg) 260.01 227.01 190.69 190.69 190.69 150.13 mhz f max_nopipelinereg_patdet without pipeline registers (mreg, adreg) with pattern detect 241.72 211.15 177.43 177.43 177.43 140.10 mhz table 32: global clock switching charac teristics (including bufgctrl) symbol description speed grade units 1.0v 0.95v 0.9v -3 -2/-2le -1 -1q/-1m -1li -2le t bccck_ce / t bcckc_ce (1) ce pins setup/hold 0.12/0.39 0.13/0.40 0. 16/0.41 0.16/0.83 0. 16/0.41 0.31/0.67 ns t bccck_s / t bcckc_s (1) s pins setup/hold 0.12/0.3 9 0.13/0.40 0.16/0.41 0.16/ 0.83 0.16/0.41 0.31/0.67 ns t bccko_o (2) bufgctrl delay from i0/i1 to o 0.08 0.09 0.10 0.10 0.10 0.14 ns maximum frequency f max_bufg global clock tree (bufg) 628.00 628.00 464.00 464.00 464.00 394.00 mhz notes: 1. t bccck_ce and t bcckc_ce must be satisfied to assure glitch-free operation of the global clock when switching between clocks. these parameters do not apply to the bufgmux primitive that assures glitch-free operation. the other global clock setup and hold time s are optional; only needing to be satisfied if device operation requires simulation matc hes on a cycle-for-cycle basis when switchin g between clocks. 2. t bgcko_o (bufg delay from i0 to o) values are the same as t bccko_o values. table 33: input/output clock switching characteristics (bufio) symbol description speed grade units 1.0v 0.95v 0.9v -3 -2/-2le -1 -1q/-1m -1li -2le t biocko_o clock to out delay from i to o 1.11 1.26 1.54 1.54 1.54 1.56 ns maximum frequency f max_bufio i/o clock tree (bufio) 680.00 680.00 600.00 600.00 600.00 600.00 mhz table 34: regional clock buffer swit ching characteristics (bufr) symbol description speed grade units 1.0v 0.95v 0.9v -3 -2/-2le -1 -1q/-1m -1li -2le t brcko_o clock to out delay from i to o 0.64 0.76 0.99 0.99 0.99 1.24 ns t brcko_o_byp clock to out delay from i to o with divide bypass attribute set 0.34 0.39 0.52 0.52 0.52 0.72 ns t brdo_o propagation delay from clr to o 0.81 0.85 1.09 1.09 1.09 0.96 ns table 31: dsp48e1 switching characteristics (cont?d) symbol description speed grade units 1.0v 0.95v 0.9v -3 -2/-2le -1 -1q/-1m -1li -2le s e n d f e e d b a c k
artix-7 fpgas data sheet: dc and ac switching characteristics ds181 (v1.21) september 27, 2016 www.xilinx.com product specification 36 maximum frequency f max_bufr (1) regional clock tree (bufr) 420.00 375.00 315.00 315.00 315.00 315.00 mhz notes: 1. the maximum input frequency to the bufr and bufmr is the bufio f max frequency. table 35: horizontal clock buffer swit ching characteristics (bufh) symbol description speed grade units 1.0v 0.95v 0.9v -3 -2/-2le -1 -1q/-1m -1li -2le t bhcko_o bufh delay from i to o 0.10 0.11 0.13 0.13 0.13 0.16 ns t bhcck_ce / t bhckc_ce ce pin setup and hold 0.19/0.13 0.22/0.15 0 .28/0.21 0.28/0.42 0.28/0.21 0.35/0.25 ns maximum frequency f max_bufh horizontal clock buffer (bufh) 62 8.00 628.00 464.00 464.00 464.00 394.00 mhz table 36: duty cycle distortion and clock-tree skew symbol description device speed grade units 1.0v 0.95v 0.9v -3 -2/-2le -1 -1q/-1m -1li -2le t dcd_clk global clock tree duty-cycle distortion (1) all 0.20 0.20 0.20 n/a 0.20 0.25 ns t ckskew global clock tree skew (2) xc7a12t 0.26 0.26 0.26 n/a 0.26 ns xc7a15t 0.26 0.26 0.26 n/a 0.26 0.33 ns xc7a25t 0.26 0.26 0.26 n/a 0.26 ns xc7a35t 0.26 0.26 0.26 n/a 0.26 0.33 ns xc7a50t 0.26 0.26 0.26 n/a 0.26 0.33 ns xc7a75t 0.27 0.33 0.36 n/a 0.36 0.48 ns xc7a100t 0.27 0.33 0.36 n/a 0.36 0.48 ns xc7a200t 0.40 0.48 0.54 n/a 0.54 0.69 ns xa7a15t n/a 0.26 0.26 0.26 n/a n/a ns xa7a35t n/a 0.26 0.26 0.26 n/a n/a ns xa7a50t n/a 0.26 0.26 0.26 n/a n/a ns xa7a75t n/a 0.33 0.36 0.36 n/a n/a ns xa7a100t n/a 0.33 0.36 0.36 n/a n/a ns xq7a50t n/a 0.26 0.26 0.26 0.26 n/a ns xq7a100t n/a 0.33 0.36 0.36 0.36 n/a ns xq7a200t n/a 0.48 0.54 0.54 0.54 n/a ns t dcd_bufio i/o clock tree duty cycle distortion all 0.14 0.14 0.14 0.14 0.14 0.14 ns t bufioskew i/o clock tree skew across one clock region all 0.03 0.03 0.03 0.03 0.03 0.03 ns table 34: regional clock buffer switch ing characteristics (bufr) (cont?d) symbol description speed grade units 1.0v 0.95v 0.9v -3 -2/-2le -1 -1q/-1m -1li -2le s e n d f e e d b a c k
artix-7 fpgas data sheet: dc and ac switching characteristics ds181 (v1.21) september 27, 2016 www.xilinx.com product specification 37 mmcm switching characteristics t dcd_bufr regional clock tree duty cycle distortion all 0.18 0.18 0.18 0.18 0.18 0.18 ns notes: 1. these parameters represent the worst-case duty cycle distortion observable at the i/o flip flops. for all i/o standards, ibis can be used to calculate any additional duty cycle distortion that might be caused by asymmetrical rise/fall times. 2. the t ckskew value represents the worst-case clock-tree skew observable between sequential i/o elements. significantly less clock-tree skew exists for i/o registers that are close to each other and fed by the same or adjacent clock-tree branches. use the xilinx timing analyzer tools to evaluate clock skew specific to your application. table 37: mmcm specification symbol description speed grade units 1.0v 0.95v 0.9v -3 -2/-2le -1 -1li -2le mmcm_f inmax maximum input clock frequency 800.00 800.00 800.00 800.00 800.00 mhz mmcm_f inmin minimum input clock frequency 10.00 10.00 10.00 10.00 10.00 mhz mmcm_f injitter maximum input clock period jitter < 20% of clock input period or 1 ns max mmcm_f induty allowable input duty cycle: 10?49 mhz 25 25 25 25 25 % allowable input duty cycle: 50?199 mhz 30 30 30 30 30 % allowable input duty cycle: 200?399 mhz 35 35 35 35 35 % allowable input duty cycle: 400?499 mhz 40 40 40 40 40 % allowable input duty cycle: > 500 mhz 45 45 45 45 45 % mmcm_f min_psclk minimum dynamic phase-shift clock frequency 0.01 0.01 0.01 0.01 0.01 mhz mmcm_f max_psclk maximum dynamic phase-shift clock frequency 550.00 500.00 450.00 450.00 450.00 mhz mmcm_f vcomin minimum mmcm vco frequency 600.00 600.00 600.00 600.00 600.00 mhz mmcm_f vcomax maximum mmcm vco frequency 1600.00 1440.00 1200.00 1200.00 1200.00 mhz mmcm_f bandwidth low mmcm bandwidth at typical (1) 1.00 1.00 1.00 1.00 1.00 mhz high mmcm bandwidth at typical (1) 4.00 4.00 4.00 4.00 4.00 mhz mmcm_t statphaoffset static phase offset of the mmcm outputs (2) 0.12 0.12 0.12 0.12 0.12 ns mmcm_t outjitter mmcm output jitter note 3 mmcm_t outduty mmcm output clock duty-cycle precision (4) 0.20 0.20 0.20 0.20 0.25 ns mmcm_t lockmax mmcm maximum lock time 100.00 100.00 100.00 100.00 100.00 s mmcm_f outmax mmcm maximum output frequency 8 00.00 800.00 800.00 800.00 800.00 mhz mmcm_f outmin mmcm minimum output frequency (5)(6) 4.69 4.69 4.69 4.69 4.69 mhz mmcm_t extfdvar external clock feedback variation < 20% of clock input period or 1 ns max table 36: duty cycle distortion and clock-tree skew (cont?d) symbol description device speed grade units 1.0v 0.95v 0.9v -3 -2/-2le -1 -1q/-1m -1li -2le s e n d f e e d b a c k
artix-7 fpgas data sheet: dc and ac switching characteristics ds181 (v1.21) september 27, 2016 www.xilinx.com product specification 38 mmcm_rst minpulse minimum reset pulse width 5.00 5.00 5.00 5.00 5.00 ns mmcm_f pfdmax maximum frequency at the phase frequency detector 550.00 500.00 450.00 450.00 450.00 mhz mmcm_f pfdmin minimum frequency at the phase frequency detector 10.00 10.00 10.00 10.00 10.00 mhz mmcm_t fbdelay maximum delay in the feedback path 3 ns max or one clkin cycle mmcm switching characteristics setup and hold t mmcmdck_psen / t mmcmckd_psen setup and hold of phase-shift enable 1.04/0. 00 1.04/0.00 1.04/0.00 1 .04/0.00 1.04/0.00 ns t mmcmdck_psincdec / t mmcmckd_psincdec setup and hold of phase-shift increment/decrement 1.04/0.00 1.04/0.00 1.04/0 .00 1.04/0.00 1.04/0.00 ns t mmcmcko_psdone phase shift clock-to-out of psdone 0.59 0.68 0.81 0.81 0.78 ns dynamic reconfiguration port (drp ) for mmcm before and after dclk t mmcmdck_daddr / t mmcmckd_daddr daddr setup/hold 1.25/0.15 1.40/0.15 1.63 /0.15 1.63/0.15 1.43/0.00 ns, min t mmcmdck_di / t mmcmckd_di di setup/hold 1.25/0.15 1.40/0.15 1. 63/0.15 1.63/0.15 1.43/0.00 ns, min t mmcmdck_den / t mmcmckd_den den setup/hold 1.76/0.00 1.97/0.00 2.29 /0.00 2.29/0.00 2.40/0.00 ns, min t mmcmdck_dwe / t mmcmckd_dwe dwe setup/hold 1.25/0.15 1.40/0.15 1.63 /0.15 1.63/0.15 1.43/0.00 ns, min t mmcmcko_drdy clk to out of drdy 0.65 0.72 0.99 0.99 0.99 ns, max f dck dclk frequency 200.00 200.00 200.00 200.00 100.00 mhz, max notes: 1. the mmcm does not filter typical spread-spectrum input clocks because they are usually far below the bandwidth filter frequen cies. 2. the static offset is measured between any mmcm outputs with identical phase. 3. values for this parameter are available in the clocking wizard. see http://www.xilinx.c om/products/intell ectual-property/cl ocking_wizard.htm . 4. includes global clock buffer. 5. calculated as f vco /128 assuming output duty cycle is 50%. 6. when clkout4_cascade = true, mmcm_f outmin is 0.036 mhz. table 37: mmcm specification (cont?d) symbol description speed grade units 1.0v 0.95v 0.9v -3 -2/-2le -1 -1li -2le s e n d f e e d b a c k
artix-7 fpgas data sheet: dc and ac switching characteristics ds181 (v1.21) september 27, 2016 www.xilinx.com product specification 39 pll switching characteristics table 38: pll specification symbol description speed grade units 1.0v 0.95v 0.9v -3 -2/-2le -1 -1li -2le pll_f inmax maximum input clock frequency 800.00 800.00 800.00 800.00 800.00 mhz pll_f inmin minimum input clock frequency 19.00 19.00 19.00 19.00 19.00 mhz pll_f injitter maximum input clock period jitter < 20% of clock input period or 1 ns max pll_f induty allowable input duty cycle: 19?49 mhz 25 25 25 25 25 % allowable input duty cycle: 50?199 mhz 30 30 30 30 30 % allowable input duty cycle: 200?399 mhz 35 35 35 35 35 % allowable input duty cycle: 400?499 mhz 40 40 40 40 40 % allowable input duty cycle: >500 mhz 45 45 45 45 45 % pll_f vcomin minimum pll vco frequency 800.00 800.00 800.00 800.00 800.00 mhz pll_f vcomax maximum pll vco frequency 2133.00 1866.00 1600.00 1600.00 1600.00 mhz pll_f bandwidth low pll bandwidth at typical (1) 1.00 1.00 1.00 1.00 1.00 mhz high pll bandwidth at typical (1) 4.00 4.00 4.00 4.00 4.00 mhz pll_t statphaoffset static phase offset of the pll outputs (2) 0.12 0.12 0.12 0.12 0.12 ns pll_t outjitter pll output jitter note 3 pll_t outduty pll output clock duty-cycle precision (4) 0.20 0.20 0.20 0.20 0.25 ns pll_t lockmax pll maximum lock time 100.00 100.00 100.00 100.00 100.00 s pll_f outmax pll maximum output frequency 8 00.00 800.00 800.00 800.00 800.00 mhz pll_f outmin pll minimum output frequency (5) 6.25 6.25 6.25 6.25 6.25 mhz pll_t extfdvar external clock feedback variation < 20% of clock input period or 1 ns max pll_rst minpulse minimum reset pulse width 5.00 5.00 5.00 5.00 5.00 ns pll_f pfdmax maximum frequency at the phase frequency detector 550.00 500.00 450.00 450.00 450.00 mhz pll_f pfdmin minimum frequency at the phase frequency detector 19.00 19.00 19.00 19.00 19.00 mhz pll_t fbdelay maximum delay in the feedback path 3 ns max or one clkin cycle dynamic reconfiguration port (drp ) for pll before and after dclk t plldck_daddr / t pllckd_daddr setup and hold of d address 1.25/0.15 1.40/ 0.15 1.63/0.15 1.63/0.15 1.43/0.00 ns, min t plldck_di / t pllckd_di setup and hold of d input 1.25/0.15 1.40/ 0.15 1.63/0.15 1.63/0.15 1.43/0.00 ns, min t plldck_den / t pllckd_den setup and hold of d enable 1.76/0.00 1.97/ 0.00 2.29/0.00 2.29/0.00 2.40/0.00 ns, min t plldck_dwe / t pllckd_dwe setup and hold of d write enable 1.25/0.15 1 .40/0.15 1.63/0.15 1.63/ 0.15 1.43/0.00 ns, min t pllcko_drdy clk to out of drdy 0.65 0.72 0.99 0.99 0.99 ns, max s e n d f e e d b a c k
artix-7 fpgas data sheet: dc and ac switching characteristics ds181 (v1.21) september 27, 2016 www.xilinx.com product specification 40 device pin-to-pin output parameter guidelines f dck dclk frequency 200.00 200.00 200.00 200.00 100.00 mhz, max notes: 1. the pll does not filter typical spread-spectrum input clocks because they are usually far below the bandwidth filter frequenc ies. 2. the static offset is measured between any pll outputs with identical phase. 3. values for this parameter are available in the clocking wizard. see http://www.xilinx.c om/products/intell ectual-property/cl ocking_wizard.htm . 4. includes global clock buffer. 5. calculated as f vco /128 assuming output duty cycle is 50%. table 39: clock-capable clock input to output de lay without mmcm/pll (near clock region) (1) symbol description device speed grade units 1.0v 0.95v 0.9v -3 -2/-2le -1 -1m/-1q -1li -2le sstl15 clock-capable clock input to output dela y using output flip-flop, fast slew rate, without mmcm/pll. t ickof clock-capable clock input and outff at pins/banks closest to the bufgs without mmcm/pll (near clock region) (2) xc7a12t 4.97 5.55 6.44 n/a 6.44 ns xc7a15t 5.10 5.70 6.61 n/a 6.61 7.56 ns xc7a25t 4.97 5.55 6.44 n/a 6.44 ns xc7a35t 5.10 5.70 6.61 n/a 6.61 7.56 ns xc7a50t 5.10 5.70 6.61 n/a 6.61 7.56 ns xc7a75t 5.14 5.74 6.72 n/a 6.72 7.62 ns xc7a100t 5.14 5.74 6.72 n/a 6.72 7.62 ns xc7a200t 5.47 6.11 7.16 n/a 7.16 8.08 ns xa7a15t n/a 5.70 6.61 6.61 n/a n/a ns xa7a35t n/a 5.70 6.61 6.61 n/a n/a ns xa7a50t n/a 5.70 6.61 6.61 n/a n/a ns xa7a75t n/a 5.74 6.72 6.72 n/a n/a ns xa7a100t n/a 5.74 6.72 6.72 n/a n/a ns xq7a50t n/a 5.70 6.61 6.61 6.61 n/a ns xq7a100t n/a 5.74 6.72 6.72 6.72 n/a ns xq7a200t n/a 6.11 7.16 7.16 7.16 n/a ns notes: 1. listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible iob and clb flip-flops are clocked by the global clock net. 2. refer to the die level bank numbering overview section of 7 series fpga packaging and pinout specification ( ug475 ). table 38: pll specification (cont?d) symbol description speed grade units 1.0v 0.95v 0.9v -3 -2/-2le -1 -1li -2le s e n d f e e d b a c k
artix-7 fpgas data sheet: dc and ac switching characteristics ds181 (v1.21) september 27, 2016 www.xilinx.com product specification 41 table 40: clock-capable clock input to output de lay without mmcm/pll (far clock region) (1) symbol description device speed grade units 1.0v 0.95v 0.9v -3 -2/-2le -1 -1m/-1q -1li -2le sstl15 clock-capable clock input to output dela y using output flip-flop, fast slew rate, without mmcm/pll. t ickoffar clock-capable clock input and outff at pins/banks farthest from the bufgs without mmcm/pll (far clock region) (2) xc7a12t 4.97 5.55 6.44 n/a 6.44 ns xc7a15t 5.10 5.70 6.61 n/a 6.61 7.57 ns xc7a25t 4.97 5.55 6.44 n/a 6.44 ns xc7a35t 5.10 5.70 6.61 n/a 6.61 7.57 ns xc7a50t 5.10 5.70 6.61 n/a 6.61 7.57 ns xc7a75t 5.38 6.01 7.02 n/a 7.02 7.94 ns xc7a100t 5.38 6.01 7.02 n/a 7.02 7.94 ns xc7a200t 6.17 6.89 8.05 n/a 8.05 9.03 ns xa7a15t n/a 5.70 6.61 6.61 n/a n/a ns xa7a35t n/a 5.70 6.61 6.61 n/a n/a ns xa7a50t n/a 5.70 6.61 6.61 n/a n/a ns xa7a75t n/a 6.01 7.02 7.02 n/a n/a ns xa7a100t n/a 6.01 7.02 7.02 n/a n/a ns xq7a50t n/a 5.70 6.61 6.61 6.61 n/a ns xq7a100t n/a 6.01 7.02 7.02 7.02 n/a ns xq7a200t n/a 6.89 8.05 8.05 8.05 n/a ns notes: 1. listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible iob and clb flip-flops are clocked by the global clock net. 2. refer to the die level bank numbering overview section of 7 series fpga packaging and pinout specification ( ug475 ). s e n d f e e d b a c k
artix-7 fpgas data sheet: dc and ac switching characteristics ds181 (v1.21) september 27, 2016 www.xilinx.com product specification 42 table 41: clock-capable clock input to output delay with mmcm symbol description device speed grade units 1.0v 0.95v 0.9v -3 -2/-2le -1 -1m/-1q -1li -2le sstl15 clock-capable clock input to output dela y using output flip-flop, fast slew rate, with mmcm. t ickofmmcmcc clock-capable clock input and outff with mmcm xc7a12t 1.00 1.00 1.00 n/a 1.00 ns xc7a15t 1.00 1.00 1.00 n/a 1.00 1.78 ns xc7a25t 1.00 1.00 1.00 n/a 1.00 ns xc7a35t 1.00 1.00 1.00 n/a 1.00 1.78 ns xc7a50t 1.00 1.00 1.00 n/a 1.00 1.78 ns xc7a75t 1.00 1.00 1.00 n/a 1.00 1.79 ns xc7a100t 1.00 1.00 1.00 n/a 1.00 1.79 ns xc7a200t 1.01 1.02 1.04 n/a 1.04 1.84 ns xa7a15t n/a 1.00 1.00 1.00 n/a n/a ns xa7a35t n/a 1.00 1.00 1.00 n/a n/a ns xa7a50t n/a 1.00 1.00 1.00 n/a n/a ns xa7a75t n/a 1.00 1.00 1.00 n/a n/a ns xa7a100t n/a 1.00 1.00 1.00 n/a n/a ns xq7a50t n/a 1.00 1.00 1.00 1.00 n/a ns xq7a100t n/a 1.00 1.00 1.00 1.00 n/a ns xq7a200t n/a 1.02 1.04 1.04 1.04 n/a ns notes: 1. listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible iob and clb flip-flops are clocked by the global clock net. 2. mmcm output jitter is already included in the timing calculation. s e n d f e e d b a c k
artix-7 fpgas data sheet: dc and ac switching characteristics ds181 (v1.21) september 27, 2016 www.xilinx.com product specification 43 table 42: clock-capable clock input to output delay with pll symbol description device speed grade units 1.0v 0.95v 0.9v -3 -2/-2le -1 -1m/-1q -1li -2le sstl15 clock-capable clock input to output dela y using output flip-flop, fast slew rate, with pll. t ickofpllcc clock-capable clock input and outff with pll xc7a12t 0.83 0.83 0.83 n/a 0.83 ns xc7a15t 0.82 0.82 0.82 n/a 0.82 1.39 ns xc7a25t 0.83 0.83 0.83 n/a 0.83 ns xc7a35t 0.82 0.82 0.82 n/a 0.82 1.39 ns xc7a50t 0.82 0.82 0.82 n/a 0.82 1.39 ns xc7a75t 0.82 0.82 0.82 n/a 0.82 1.40 ns xc7a100t 0.82 0.82 0.82 n/a 0.82 1.40 ns xc7a200t 0.81 0.81 0.81 n/a 0.81 1.45 ns xa7a15t n/a 0.82 0.82 0.82 n/a n/a ns xa7a35t n/a 0.82 0.82 0.82 n/a n/a ns xa7a50t n/a 0.82 0.82 0.82 n/a n/a ns xa7a75t n/a 0.82 0.82 0.82 n/a n/a ns xa7a100t n/a 0.82 0.82 0.82 n/a n/a ns xq7a50t n/a 0.82 0.82 0.82 0.82 n/a ns xq7a100t n/a 0.82 0.82 0.82 0.82 n/a ns xq7a200t n/a 0.81 0.81 0.81 0.81 n/a ns notes: 1. listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible iob and clb flip-flops are clocked by the global clock net. 2. pll output jitter is already included in the timing calculation. table 43: pin-to-pin, clock-to-out using bufio symbol description speed grade units 1.0v 0.95v 0.9v -3 -2/-2le -1 -1m/-1q -1li -2le sstl15 clock-capable clock input to output delay us ing output flip-flop, fast slew rate, with bufio. t ickofcs clock to out of i/o clock 5.01 5.61 6.64 6.64 6.64 7.32 ns s e n d f e e d b a c k
artix-7 fpgas data sheet: dc and ac switching characteristics ds181 (v1.21) september 27, 2016 www.xilinx.com product specification 44 device pin-to-pin input parameter guidelines all devices are 100% functionally tested. values ar e expressed in nanosecond s unless otherwise noted. table 44: global clock input setup and hold without mmcm/pll with zhold_delay on hr i/o banks symbol description device speed grade units 1.0v 0.95v 0.9v -3 -2/-2le -1 -1m/-1q -1li -2le input setup and hold time relative to global clock input signal for sstl15 standard. (1) t psfd / t phfd full delay (legacy delay or default delay) global clock input and iff (2) without mmcm/pll with zhold_delay on hr i/o banks xc7a12t 2.48/?0.41 2.66/?0.4 1 3.11/?0.41 n/a 3.11/?0.41 ns xc7a15t 2.47/?0.29 2.65/?0.29 3.10/ ?0.29 n/a 3.10/?0. 29 5.10/?0.44 ns xc7a25t 2.48/?0.41 2.66/?0.4 1 3.11/?0.41 n/a 3.11/?0.41 ns xc7a35t 2.47/?0.29 2.65/?0.29 3.10/ ?0.29 n/a 3.10/?0. 29 5.10/?0.44 ns xc7a50t 2.47/?0.29 2.65/?0.29 3.10/ ?0.29 n/a 3.10/?0. 29 5.10/?0.44 ns xc7a75t 2.69/?0.34 2.89/?0.34 3.34/ ?0.34 n/a 3.34/?0. 34 5.66/?0.51 ns xc7a100t 2.69/?0.34 2.89/?0.34 3.3 4/?0.34 n/a 3.34/?0. 34 5.66/?0.51 ns xc7a200t 3.03/?0.36 3.27/?0.36 3.7 9/?0.36 n/a 3.79/?0. 36 6.66/?0.55 ns xa7a15t n/a 2.65/?0.29 3.10/ ?0.29 3.10/?0.29 n/a n/a ns xa7a35t n/a 2.65/?0.29 3.10/ ?0.29 3.10/?0.29 n/a n/a ns xa7a50t n/a 2.65/?0.29 3.10/ ?0.29 3.10/?0.29 n/a n/a ns xa7a75t n/a 2.89/?0.34 3.34/ ?0.34 3.34/?0.34 n/a n/a ns xa7a100t n/a 2.89/?0.34 3.34/ ?0.34 3.34/?0.34 n/a n/a ns xq7a50t n/a 2.65/?0.29 3.10/?0. 29 3.10/?0.29 3.10/?0.29 n/a ns xq7a100t n/a 2.89/?0.34 3.34/?0. 34 3.34/?0.34 3.34/?0.34 n/a ns xq7a200t n/a 3.27/?0.36 3.79/?0. 36 3.79/?0.36 3.79/?0.36 n/a ns notes: 1. setup and hold times are measured over worst case conditions (p rocess, voltage, temperature). setup time is measured relative to the global clock input signal using the slowest process, highest temperature, and lowest voltage. hold time is measured relative to the gl obal clock input signal using the fastest process, lowest temperature, and highest voltage. 2. iff = input flip-flop or latch. s e n d f e e d b a c k
artix-7 fpgas data sheet: dc and ac switching characteristics ds181 (v1.21) september 27, 2016 www.xilinx.com product specification 45 table 45: clock-capable clock input setup and hold with mmcm symbol description device speed grade units 1.0v 0.95v 0.9v -3 -2/-2le -1 -1m/-1q -1li -2le input setup and hold time relative to global clock input signal for sstl15 standard. (1) t psmmcmcc / t phmmcmcc no delay clock- capable clock input and iff (2) with mmcm xc7a12t 2.37/?0.61 2.69/?0.61 3.21/?0.61 n/a 3.21/?0.61 ns xc7a15t 2.46/?0.62 2.80/ ?0.62 3.35/?0.62 n/a 3.35/ ?0.62 2.14/?0.48 ns xc7a25t 2.37/?0.61 2.69/?0.61 3.21/?0.61 n/a 3.21/?0.61 ns xc7a35t 2.46/?0.62 2.80/ ?0.62 3.35/?0.62 n/a 3.35/ ?0.62 2.14/?0.48 ns xc7a50t 2.46/?0.62 2.80/ ?0.62 3.35/?0.62 n/a 3.35/ ?0.62 2.14/?0.48 ns xc7a75t 2.47/?0.62 2.81/ ?0.62 3.36/?0.62 n/a 3.36/ ?0.62 2.15/?0.48 ns xc7a100t 2.47/?0.62 2.81/?0.62 3.36/ ?0.62 n/a 3.36/?0.62 2.15/?0.48 ns xc7a200t 2.59/?0.63 2.95/?0.63 3.52/ ?0.63 n/a 3.52/?0.63 2.32/?0.51 ns xa7a15t n/a 2.80/?0.62 3.35/?0.62 3.35/?0.62 n/a n/a ns xa7a35t n/a 2.80/?0.62 3.35/?0.62 3.35/?0.62 n/a n/a ns xa7a50t n/a 2.80/?0.62 3.35/?0.62 3.35/?0.62 n/a n/a ns xa7a75t n/a 2.81/?0.62 3.36/?0.62 3.36/?0.62 n/a n/a ns xa7a100t n/a 2.81/?0.62 3.36/?0 .62 3.36/?0.62 n/a n/a ns xq7a50t n/a 2.80/?0.62 3.35/?0.6 2 3.35/?0.62 3.35/?0.62 n/a ns xq7a100t n/a 2.81/?0. 62 3.36/?0.62 3.36/?0.62 3.36/?0.62 n/a ns xq7a200t n/a 2.95/?0. 63 3.52/?0.63 3.52/?0.63 3.52/?0.63 n/a ns notes: 1. setup and hold times are measured over worst case conditions (pro cess, voltage, temperature). setup time is measured relative to the global clock input signal using the slowest process, highest temperature, and lowest voltage. hold time is measured relative to the global clock input signal using the fastest process, lowest temperature, and highest voltage. 2. iff = input flip-flop or latch 3. use ibis to determine any duty-cycle distortion incurred using various standards. s e n d f e e d b a c k
artix-7 fpgas data sheet: dc and ac switching characteristics ds181 (v1.21) september 27, 2016 www.xilinx.com product specification 46 table 46: clock-capable clock input setup and hold with pll symbol description device speed grade units 1.0v 0.95v 0.9v -3 -2/-2le -1 -1m/-1q -1li -2le input setup and hold time relative to clock-capable clock input signal for sstl15 standard. (1) t pspllcc / t phpllcc no delay clock-capable clock input and iff (2) with pll xc7a12t 2.68/?0.19 3.04/?0.19 3.63/?0.19 n/a 3.63/?0.19 ns xc7a15t 2.77/?0.20 3.15/?0.20 3.77/ ?0.20 n/a 3.77/?0.20 2.46/?0.59 ns xc7a25t 2.68/?0.19 3.04/?0.19 3.63/?0.19 n/a 3.63/?0.19 ns xc7a35t 2.77/?0.20 3.15/?0.20 3.77/ ?0.20 n/a 3.77/?0.20 2.46/?0.59 ns xc7a50t 2.77/?0.20 3.15/?0.20 3.77/ ?0.20 n/a 3.77/?0.20 2.46/?0.59 ns xc7a75t 2.78/?0.20 3.15/?0.20 3.78/ ?0.20 n/a 3.78/?0.20 2.47/?0.59 ns xc7a100t 2.78/?0.20 3.15/?0.20 3.78/ ?0.20 n/a 3.78/?0.20 2.47/?0.59 ns xc7a200t 2.91/?0.21 3.29/?0.21 3.94/ ?0.21 n/a 3.94/?0.21 2.64/?0.62 ns xa7a15t n/a 3.15/?0.20 3.77/?0.20 3.77/?0.20 n/a n/a ns xa7a35t n/a 3.15/?0.20 3.77/?0.20 3.77/?0.20 n/a n/a ns xa7a50t n/a 3.15/?0.20 3.77/?0.20 3.77/?0.20 n/a n/a ns xa7a75t n/a 3.15/?0.20 3.78/?0.20 3.78/?0.20 n/a n/a ns xa7a100t n/a 3.15/?0.20 3.78/ ?0.20 3.78/?0.20 n/a n/a ns xq7a50t n/a 3.15/?0.20 3.77/?0.2 0 3.77/?0.20 3.77/?0.20 n/a ns xq7a100t n/a 3.15/?0.20 3.78/?0 .20 3.78/?0.20 3. 78/?0.20 n/a ns xq7a200t n/a 3.29/?0.21 3.94/?0 .21 3.94/?0.21 3. 94/?0.21 n/a ns notes: 1. setup and hold times are measured over worst case conditions (pro cess, voltage, temperature). setup time is measured relative to the global clock input signal using the slowest process, highest temperature, and lowest voltage. hold time is measured relative to the global clock input signal using the fastest process, lowest temperature, and highest voltage. 2. iff = input flip-flop or latch 3. use ibis to determine any duty-cycle distortion incurred using various standards. table 47: data input setup and hold times relative to a forwarded clock input pin using bufio symbol description speed grade units 1.0v 0.95v 0.9v -3 -2/-2le -1 -1m/-1q -1li -2le input setup and hold time relative to a forwarded clock input pin using bufio for sstl15 standard. t pscs /t phcs setup and hold of i/o clock ?0.38/1.31 ?0.38/1 .46 ?0.38/1.76 ?0.38/1.76 ?0.38/1.76 ?0.16/1.89 ns table 48: sample window symbol description speed grade units 1.0v 0.95v 0.9v -3 -2/-2le -1 -1m/-1q -1li -2le t samp sampling error at receiver pins (1) 0.59 0.64 0.70 0.70 0.70 0.70 ns s e n d f e e d b a c k
artix-7 fpgas data sheet: dc and ac switching characteristics ds181 (v1.21) september 27, 2016 www.xilinx.com product specification 47 additional package parameter guidelines the parameters in this section provide the necessary values fo r calculating timing budgets for artix-7 fpga clock transmitter and receiver data-valid windows. t samp_bufio sampling error at receiver pins using bufio (2) 0.35 0.40 0.46 0.46 0.46 0.46 ns notes: 1. this parameter indicates the total sampling error of the arti x-7 fpgas ddr input registers, measured across voltage, temperat ure, and process. the characterization methodology uses the mmcm to captur e the ddr input registers? edges of operation. these measureme nts include: - clk0 mmcm jitter - mmcm accuracy (phase offset) - mmcm phase shift resolution these measurements do not include package or clock tree skew. 2. this parameter indicates the total sampling error of the arti x-7 fpgas ddr input registers, measured across voltage, temperat ure, and process. the characterization methodology us es the bufio clock network and idelay to capture the ddr input registers? edges of operation. these measurements do not include package or clock tree skew. table 49: package skew symbol description device package value units t pkgskew package skew (1) xc7a12t cpg236 ps csg325 ps xc7a15t cpg236 48 ps csg324 104 ps csg325 142 ps ftg256 98 ps fgg484 97 ps xc7a25t cpg236 ps csg325 ps xc7a35t cpg236 48 ps csg324 104 ps csg325 142 ps ftg256 98 ps fgg484 97 ps xc7a50t cpg236 48 ps csg324 104 ps csg325 142 ps ftg256 98 ps fgg484 97 ps xc7a75t csg324 113 ps ftg256 120 ps fgg484 144 ps fgg676 153 ps table 48: sample window (cont?d) symbol description speed grade units 1.0v 0.95v 0.9v -3 -2/-2le -1 -1m/-1q -1li -2le s e n d f e e d b a c k
artix-7 fpgas data sheet: dc and ac switching characteristics ds181 (v1.21) september 27, 2016 www.xilinx.com product specification 48 gtp transceiver specifications gtp transceiver dc input and output levels table 50 summarizes the dc output specifications of the gtp transceivers in artix-7 fpgas. consult 7 series fpgas gtp transceiver user guide ( ug482 ) for further details. t pkgskew package skew (1) xc7a100t csg324 113 ps ftg256 120 ps fgg484 144 ps fgg676 153 ps xc7a200t sbg484/sbv484 111 ps fbg484/fbv484 109 ps fbg676/fbv676 121 ps ffg1156/ffv1156 151 ps xa7a15t cpg236 48 ps csg324 104 ps csg325 142 ps xa7a35t cpg236 48 ps csg324 104 ps csg325 142 ps xa7a50t cpg236 48 ps csg324 104 ps csg325 142 ps xa7a75t csg324 113 ps fgg484 144 ps xa7a100t csg324 113 ps fgg484 144 ps xq7a50t cs325 142 ps fg484 97 ps xq7a100t cs324 113 ps fg484 144 ps xq7a200t rs484 111 ps rb484 109 ps rb676 121 ps notes: 1. these values represent the worst-case skew between any two selectio resources in the package: shortest delay to longest delay from die pad to ball. 2. package delay information is available for these device/package combinations. this information can be used to deskew the pack age. table 50: gtp transceiver dc specifications symbol dc parameter conditions min typ max units dv ppout differential peak-t o-peak output voltage (1) transmitter output swing is set to maximum setting 1000 ? ? mv v cmoutdc dc common mode output voltage equation based v mgtavtt ?dv ppout /4 mv r out differential output resistance ? 100 ? table 49: package skew (cont?d) symbol description device package value units s e n d f e e d b a c k
artix-7 fpgas data sheet: dc and ac switching characteristics ds181 (v1.21) september 27, 2016 www.xilinx.com product specification 49 note: in figure 4 , differential peak-to-peak voltage = si ngle-ended peak-to-peak voltage x 2. table 51 summarizes the dc specifications of the clock input of the gtp transceiver. consult 7 series fpgas gtp transceiver user guide ( ug482 ) for further details. v cmoutac common mode output voltage: ac coupled 1/2 v mgtavtt mv t oskew transmitter output pair (txp and txn) intra-pair skew (ff, fb, sb packages) ? ? 10 ps transmitter output pair (txp and txn) intra-pair skew (fg, ft, cs, cp packages) ? ? 12 ps dv ppin differential peak-to-peak input voltage external ac coupled 150 ? 2000 mv v in single-ended input voltage (2) dc coupled v mgtavtt = 1.2v ?200 ? v mgtavtt mv v cmin common mode input voltage dc coupled v mgtavtt = 1.2v ? 2/3 v mgtavtt ?mv r in differential input resistance ? 100 ? c ext recommended external ac coupling capacitor (3) ? 100 ? nf notes: 1. the output swing and preemphasis levels are programmable using the attributes discussed in 7 series fpgas gtp transceiver user guide ( ug482 ) and can result in values lower than reported in this table. 2. voltage measured at the pin referenced to ground. 3. other values can be used as appropriate to conform to specific protocols and standards. x-ref target - figure 3 figure 3: single-ended peak -to-peak voltage x-ref target - figure 4 figure 4: differential peak-to-peak voltage table 51: gtp transceiver clock dc input level specification symbol dc parameter min typ max units v idiff differential peak-to-peak input voltage 350 ? 2000 mv r in differential input resistance ? 100 ? c ext required external ac coupling capacitor ? 100 ? nf table 50: gtp transceiver dc specifications (cont?d) symbol dc parameter conditions min typ max units 0 +v p n d s 1 8 1_01_062014 s ingle-ended pe a k-to-pe a k volt a ge 0 +v ?v p?n d s 1 8 1_02_062014 differenti a l pe a k-to-pe a k volt a ge s e n d f e e d b a c k
artix-7 fpgas data sheet: dc and ac switching characteristics ds181 (v1.21) september 27, 2016 www.xilinx.com product specification 50 gtp transceiver switching characteristics consult 7 series fpgas gtp transceiver user guide ( ug482 ) for further information. table 52: gtp transceiver performance symbol description output divider speed grade units -3 (1.0v) -2 (1.0v) -2le (1.0v) -1 (1.0v) -1li (0.95v) -1q (1.0v) -1m (1.0v) -2le (0.9v) package type ff fb sb fg ft cs cp ff fb sb rb rs fg ft cs cp ff fb sb rb rs fg ft cs cp ff fb sb fg ft cs cp f gtpmax maximum gtp transceiver data rate 6. 6 6.25 6.6 6.25 3.75 3.75 3.75 3.75 gb/s f gtpmin minimum gtp transceiver data rate 0.500 0. 500 0.500 0.500 0.500 0.500 0.500 0.500 gb/s f gtprange pll line rate range 1 3.2?6.6 3.2?6.6 3.2?3.75 3.2?3.75 gb/s 2 1.6?3.3 1.6?3.3 1.6?3.2 1.6?3.2 gb/s 4 0.8?1.65 0.8?1.65 0.8?1.6 0.8?1.6 gb/s 8 0.5?0.825 0.5?0.825 0.5?0.8 0.5?0.8 gb/s f gtppllrange gtp transceiver pll frequency range 1.6?3.3 1.6?3.3 1.6?3.3 1.6?3.3 ghz table 53: gtp transceiver dynamic reconfiguration port (drp) switching characteristics symbol description speed grade units 1.0v 0.95v 0.9v -3 -2/-2le -1 -1li -2le f gtpdrpclk gtpdrpclk maximum frequency 175 175 156 156 125 mhz table 54: gtp transceiver reference clock switching characteristics symbol description conditions all speed grades units min typ max f gclk reference clock frequency range 60 ? 660 mhz t rclk reference clock rise time 20% ? 80% ? 200 ? ps t fclk reference clock fall time 80% ? 20% ? 200 ? ps t dcref reference clock duty cycle tr ansceiver pll only 40 ? 60 % x-ref target - figure 5 figure 5: reference clock timing parameters d s 1 8 1_0 3 _062 8 11 8 0 % 20 % t fclk t rclk s e n d f e e d b a c k
artix-7 fpgas data sheet: dc and ac switching characteristics ds181 (v1.21) september 27, 2016 www.xilinx.com product specification 51 table 55: gtp transceiver pll/lock time adaptation symbol description conditions all speed grades units min typ max t lock initial pll lock ? ? 1 ms t dlock clock recovery phase acquisition and adaptation time. after the pll is locked to the reference clock, this is the time it takes to lock the clock data recovery (cdr) to the data present at the input. ? 50,000 2.3 x10 6 ui table 56: gtp transceiver user clock switching characteristics (1) symbol description conditions speed grade units 1.0v 0.95v 0.9v -3 -2/-2le -1 -1li -2le f txout txoutclk maximum frequency 412.500 412.500 234.375 234.375 234.375 mhz f rxout rxoutclk maximum frequency 412.500 412.500 234.375 234.375 234.375 mhz f txin txusrclk maximum frequency 16-bit data path 412.500 412.500 234.375 234.375 234.375 mhz f rxin rxusrclk maximum frequency 16-bit data pa th 412.500 412.500 234.375 234.375 234.375 mhz f txin2 txusrclk2 maximum frequency 16-bit data pa th 412.500 412.500 234.375 234.375 234.375 mhz f rxin2 rxusrclk2 maximum frequency 16-bit data pa th 412.500 412.500 234.375 234.375 234.375 mhz notes: 1. clocking must be implemented as described in 7 series fpgas gtp transceiver user guide ( ug482 ). s e n d f e e d b a c k
artix-7 fpgas data sheet: dc and ac switching characteristics ds181 (v1.21) september 27, 2016 www.xilinx.com product specification 52 table 57: gtp transceiver transmitter switching characteristics symbol description cond ition min typ max units f gtptx serial data rate range 0.500 ? f gtpmax gb/s t rtx tx rise time 20%?80% ? 50 ? ps t ftx tx fall time 80%?20% ? 50 ? ps t llskew tx lane-to-lane skew (1) ? ? 500 ps v txoobvdpp electrical idle amplitude ? ? 20 mv t txoobtransition electrical idle transition time ? ? 140 ns tj 6.6 total jitter (2)(3) 6.6 gb/s ? ? 0.30 ui dj 6.6 deterministic jitter (2)(3) ? ? 0.15 ui tj 5.0 total jitter (2)(3) 5.0 gb/s ? ? 0.30 ui dj 5.0 deterministic jitter (2)(3) ? ? 0.15 ui tj 4.25 total jitter (2)(3) 4.25 gb/s ? ? 0.30 ui dj 4.25 deterministic jitter (2)(3) ? ? 0.15 ui tj 3.75 total jitter (2)(3) 3.75 gb/s ? ? 0.30 ui dj 3.75 deterministic jitter (2)(3) ? ? 0.15 ui tj 3.2 total jitter (2)(3) 3.20 gb/s (4) ??0.2ui dj 3.2 deterministic jitter (2)(3) ??0.1ui tj 3.2l total jitter (2)(3) 3.20 gb/s (5) ? ? 0.32 ui dj 3.2l deterministic jitter (2)(3) ? ? 0.16 ui tj 2.5 total jitter (2)(3) 2.5 gb/s (6) ? ? 0.20 ui dj 2.5 deterministic jitter (2)(3) ? ? 0.08 ui tj 1.25 total jitter (2)(3) 1.25 gb/s (7) ? ? 0.15 ui dj 1.25 deterministic jitter (2)(3) ? ? 0.06 ui tj 500 total jitter (2)(3) 500 mb/s ??0.1ui dj 500 deterministic jitter (2)(3) ? ? 0.03 ui notes: 1. using same refclk input with tx phase alignment enabled for up to four consecutive transmitters (one fully populated gtp quad ). 2. using pll[0/1]_fbdiv = 2, 20-bit internal data width. these values are not intended for protocol specific compliance determinat ions. 3. all jitter values are based on a bit-error ratio of 1e -12 . 4. pll frequency at 3.2 ghz and txout_div = 2. 5. pll frequency at 1.6 ghz and txout_div = 1. 6. pll frequency at 2.5 ghz and txout_div = 2. 7. pll frequency at 2.5 ghz and txout_div = 4. s e n d f e e d b a c k
artix-7 fpgas data sheet: dc and ac switching characteristics ds181 (v1.21) september 27, 2016 www.xilinx.com product specification 53 table 58: gtp transceiver receiver switching characteristics symbol description min typ max units f gtprx serial data rate rx oversampler not enabled 0.500 ? f gtpmax gb/s t rxelecidle time for rxelecidle to respond to loss or restoration of data ? 10 ? ns rx oobvdpp oob detect threshold peak-to-peak 60 ? 150 mv rx sst receiver spread-spectrum tracking (1) modulated @ 33 khz ?5000 ? 5000 ppm rx rl run length (cid) ? ? 512 ui rx ppmtol data/refclk ppm offset tolerance ?1250 ? 1250 ppm sj jitter tolerance (2) jt_sj 6.6 sinusoidal jitter (3) 6.6 gb/s 0.44 ? ? ui jt_sj 5.0 sinusoidal jitter (3) 5.0 gb/s 0.44 ? ? ui jt_sj 4.25 sinusoidal jitter (3) 4.25 gb/s 0.44 ? ? ui jt_sj 3.75 sinusoidal jitter (3) 3.75 gb/s 0.44 ? ? ui jt_sj 3.2 sinusoidal jitter (3) 3.2 gb/s (4) 0.45 ? ? ui jt_sj 3.2l sinusoidal jitter (3) 3.2 gb/s (5) 0.45 ? ? ui jt_sj 2.5 sinusoidal jitter (3) 2.5 gb/s (6) 0.5 ? ? ui jt_sj 1.25 sinusoidal jitter (3) 1.25 gb/s (7) 0.5 ? ? ui jt_sj 500 sinusoidal jitter (3) 500 mb/s 0.4 ? ? ui sj jitter tolerance with stressed eye (2) jt_tjse 3.2 total jitter with stressed eye (8) 3.2 gb/s 0.70 ? ? ui jt_tjse 6.6 6.6 gb/s 0.70 ? ? ui jt_sjse 3.2 sinusoidal jitter with stressed eye (8) 3.2 gb/s 0.1 ? ? ui jt_sjse 6.6 6.6 gb/s 0.1 ? ? ui notes: 1. using rxout_div = 1, 2, and 4. 2. all jitter values are based on a bit error ratio of 1e ?12 . 3. the frequency of the injected sinusoidal jitter is 10 mhz. 4. pll frequency at 3.2 ghz and rxout_div = 2. 5. pll frequency at 1.6 ghz and rxout_div = 1. 6. pll frequency at 2.5 ghz and rxout_div = 2. 7. pll frequency at 2.5 ghz and rxout_div = 4. 8. composite jitter. s e n d f e e d b a c k
artix-7 fpgas data sheet: dc and ac switching characteristics ds181 (v1.21) september 27, 2016 www.xilinx.com product specification 54 gtp transceiver protocol jitter characteristics for table 59 through table 63 , the 7 series fpgas gtp transceiver user guide ( ug482 ) contains recommended settings for optimal usage of protocol specific characteristics. table 59: gigabit ethernet protocol characteristics description line rate (mb/s) min max units gigabit ethernet transmitter jitter generation total transmitter jitter (t_tj) 1250 ? 0.24 ui gigabit ethernet receiver high frequency jitter tolerance total receiver jitter tolerance 1250 0.749 ? ui table 60: xaui protocol characteristics description line rate (mb/s) min max units xaui transmitter jitter generation total transmitter jitter (t_tj) 3125 ? 0.35 ui xaui receiver high freq uency jitter tolerance total receiver jitter tolerance 3125 0.65 ? ui table 61: pci express protocol characteristics (1) standard description line rate (mb/s) min max units pci express transmitter jitter generation pci express gen 1 total transmitter jitter 2500 ? 0.25 ui pci express gen 2 total transmitter jitter 5000 ? 0.25 ui pci express receiver high frequency jitter tolerance pci express gen 1 total receiver jitter tolerance 2500 0.65 ? ui pci express gen 2 (2) receiver inherent timing error 5000 0.40 ? ui receiver inherent deterministic timing error 0.30 ? ui notes: 1. tested per card electromechanical (cem) methodology. 2. using common refclk. table 62: cei-6g protocol characteristics description line rate (m b/s) interface min max units cei-6g transmitter jitter generation total transmitter jitter (1) 4976?6375 cei-6g-sr ? 0.3 ui cei-6g receiver high fr equency jitter tolerance total receiver jitter tolerance (1) 4976?6375 cei-6g-sr 0.6 ? ui notes: 1. tested at most commonly used line rate of 6250 mb/s using 390.625 mhz reference clock. s e n d f e e d b a c k
artix-7 fpgas data sheet: dc and ac switching characteristics ds181 (v1.21) september 27, 2016 www.xilinx.com product specification 55 integrated interface block for pci expr ess designs switching characteristics more information and documentat ion on solutions for pci express designs can be found at: www.xilinx.com/products/te chnology/pci-express.html table 63: cpri protocol characteristics description line rate (mb/s) min max units cpri transmitter jitter generation total transmitter jitter 614.4 ? 0.35 ui 1228.8 ? 0.35 ui 2457.6 ? 0.35 ui 3072.0 ? 0.35 ui 4915.2 ? 0.3 ui 6144.0 ? 0.3 ui cpri receiver frequency jitter tolerance total receiver jitter tolerance 614.4 0.65 ? ui 1228.8 0.65 ? ui 2457.6 0.65 ? ui 3072.0 0.65 ? ui 4915.2 (1) 0.60 ? ui 6144.0 (1) 0.60 ? ui notes: 1. tested to cei-6g-sr. table 64: maximum performance for pci express designs symbol description speed grade units 1.0v 0.95v 0.9v -3 -2/-2le -1 -1li -2le f pipeclk pipe clock maximum frequency 250. 00 250.00 250.00 250.00 250.00 mhz f userclk user clock maximum frequency 250.00 250.00 250.00 250.00 250.00 mhz f userclk2 user clock 2 maximum frequency 250.00 250.00 250.00 250.00 250.00 mhz f drpclk drp clock maximum frequency 250.00 250.00 250.00 250.00 250.00 mhz notes: 1. refer to pg054 , 7 series fpgas integrated block for pci express product guide for specific supported core configurations. s e n d f e e d b a c k
artix-7 fpgas data sheet: dc and ac switching characteristics ds181 (v1.21) september 27, 2016 www.xilinx.com product specification 56 xadc specifications table 65: xadc specifications parameter symbol comments/conditions min typ max units v ccadc = 1.8v 5%, v refp = 1.25v, v refn = 0v, adcclk = 26 mhz, ?55c tj 125c, typical values at t j =+40c adc accuracy (1) resolution 12 ? ? bits integral nonlinearity (2) inl ?40c t j 100c ? ? 2 lsbs ?55c t j < ?40c; 100c < t j 125c ? ? 3 lsbs differential nonlinearity dnl no missing codes, guaranteed monotonic ? ? 1 lsbs offset error unipolar ?40c t j 100c ? ? 8 lsbs ?55c t j < ?40c; 100c < t j 125c ? ? 12 lsbs bipolar ?55c t j 125c ? ? 4 lsbs gain error ??0.5 % offset matching ? ? 4 lsbs gain matching ??0.3 % sample rate ?? 1 ms/s signal to noise ratio (2) snr f sample = 500ks/s, f in =20khz 60 ? ? db rms code noise external 1.25v reference ? ? 2 lsbs on-chip reference ? 3 ? lsbs total harmonic distortion (2) thd f sample = 500ks/s, f in =20khz 70 ? ? db analog inputs (3) adc input ranges unipolar operation 0 ? 1 v bipolar operation ?0.5 ? +0.5 v unipolar common mode range (fs input) 0 ? +0.5 v bipolar common mode range (fs input) +0.5 ? +0.6 v maximum external channel input ranges adjacent analog channels set within these ranges should not corrupt measurements on adjacent channels ?0.1 ? v ccadc v auxiliary channel full resolution bandwidth frbw 250 ? ? khz on-chip sensors temperature sensor error ?40c t j 100c ? ? 4 c ?55c t j < ?40c; 100c < t j 125c ? ? 6 c supply sensor error ?40c t j 100c ? ? 1 % ?55c t j < ?40c; 100c < t j 125c ? ? 2 % conversion rate (4) conversion time - continuous t conv number of adcclk cycles 26 ? 32 cycles conversion time - event t conv number of clk cycles ? ? 21 cycles drp clock frequency dclk drp clock frequency 8 ? 250 mhz adc clock frequency adcclk derived from dclk 1 ? 26 mhz dclk duty cycle 40 ? 60 % s e n d f e e d b a c k
artix-7 fpgas data sheet: dc and ac switching characteristics ds181 (v1.21) september 27, 2016 www.xilinx.com product specification 57 configuration switching characteristics xadc reference (5) external reference v refp externally supplied reference voltage 1.20 1.25 1.30 v on-chip reference ground v refp pin to agnd, ?40c t j 100c 1.2375 1.25 1.2625 v ground v refp pin to agnd, ?55c t j < ?40c; 100c < t j 125c 1.225 1.25 1.275 v notes: 1. offset and gain errors are removed by enabling the xadc automatic gain calibration feature. the values are specified for when this feature is enabled. 2. only specified for bitstream option xadcenhancedlinearity = on. 3. see the adc chapter in the 7 series fpgas and zynq-7000 ap soc xadc dual 12-bit 1 msps analog-to-digital converter ( ug480 ) for a detailed description. 4. see the timing chapter in the 7 series fpgas and zynq-7000 ap soc xadc dual 12-bit 1 msps analog-to-digital converter ( ug480 ) for a detailed description. 5. any variation in the reference voltage from the nominal v refp = 1.25v and v refn = 0v will result in a deviation from the ideal transfer function. this also impacts the accuracy of the internal sensor measurements (i.e., temperature and power supply). however, for external ratiometric type applications allowing reference to vary by 4% is permitted. table 66: configuration switching characteristics symbol description speed grade units 1.0v 0.95v 0.9v -3 -2/-2le -1 -1li -2le power-up timing characteristics t pl (1) program latency 5.00 5.00 5.00 5.00 5.00 ms, max t por (1) power-on reset (50 ms ramp rate time) 10/50 10/50 10/50 10/50 10/50 ms, min/max power-on reset (1 ms ramp rate time) 10/35 10/35 10/35 10/35 10/35 ms, min/max t program program pulse width 250.00 250.00 250.00 250.00 250.00 ns, min cclk output (master mode) t icck master cclk output delay 150.00 150.00 150.00 150.00 150.00 ns, min t mcckl master cclk clock low time duty cycl e 40/60 40/60 40/60 40/60 40/60 %, min/max t mcckh master cclk clock high time duty cycle 40/60 40/60 40/60 40/60 40/60 %, min/max f mcck master cclk frequency 100.00 100.0 0 100.00 100.00 70.00 mhz, max master cclk frequency for aes encrypted x16 50.00 50.00 50.00 50.00 35.00 mhz, max f mcck_start master cclk frequency at start of conf iguration 3.00 3.00 3.00 3.00 3.00 mhz, typ f mccktol frequency tolerance, master mode with respect to nominal cclk 50 50 50 50 50 %, max cclk input (slave modes) t scckl slave cclk clock minimum low time 2.50 2.50 2.50 2.50 2.50 ns, min t scckh slave cclk clock minimum high time 2.50 2.50 2.50 2.50 2.50 ns, min f scck slave cclk frequency 100.00 100.00 100.00 100.00 70.00 mhz, max emcclk input (master mode) t emcckl external master cclk low time 2.50 2.50 2.50 2.50 2.50 ns, min t emcckh external master cclk high time 2.50 2.50 2.50 2.50 2.50 ns, min f emcck external master cclk frequency 100.00 100.00 100.00 100.00 70.00 mhz, max table 65: xadc specifications (cont?d) parameter symbol comments/conditions min typ max units s e n d f e e d b a c k
artix-7 fpgas data sheet: dc and ac switching characteristics ds181 (v1.21) september 27, 2016 www.xilinx.com product specification 58 internal configuration access port f icapck internal configurati on access port (icape2) clock frequency 100.00 100.00 100.00 100.00 70.00 mhz, max master/slave serial mode programming switching t dcck / t cckd din setup/hold 4.00/0.00 4.00/0.00 4. 00/0.00 4.00/0.00 5.00/0.00 ns, min t cco dout clock to out 8.00 8.00 8.00 8.00 9.00 ns, max selectmap mode programming switching t smdcck / t smcckd d[31:00] setup/hold 4.00/0.00 4.00/0. 00 4.00/0.00 4.00/0.00 4.50/0.00 ns, min t smcscck / t smcckcs csi_b setup/hold 4.00/0.00 4.00/0.00 4.00/0.00 4.00/0.00 5.00/0.00 ns, min t smwcck / t smcckw rdwr_b setup/hold 10.00/0.00 10.00/0.00 10.00/0.00 10.00/0.00 12.00/0.00 ns, min t smckcso cso_b clock to out (330 pull-up resistor required) 7.00 7.00 7.00 7.00 8.00 ns, max t smco d[31:00] clock to out in readback 8.00 8.00 8.00 8.00 10.00 ns, max f rbcck readback frequency 100.00 100.00 100.00 100.00 70.00 mhz, max boundary-scan port ti ming specifications t taptck / t tcktap tms and tdi setup/hold 3.00/2.00 3.00/2 .00 3.00/2.00 3.00/2. 00 3.00/2.00 ns, min t tcktdo tck falling edge to tdo output 7.00 7.00 7.00 7.00 8.50 ns, max f tck tck frequency 66.00 66.00 66.00 66.00 50.00 mhz, max bpi flash master mode programming switching t bpicco (2) a[28:00], rs[1:0], fc s_b, foe_b, fwe_b, adv_b clock to out 8.50 8.50 8.50 8.50 10.00 ns, max t bpidcc / t bpiccd d[15:00] setup/hold 4.00/0.00 4.00/0. 00 4.00/0.00 4.00/0.00 4.50/0.00 ns, min spi flash master mode programming switching t spidcc / t spiccd d[03:00] setup/hold 3.00/0.00 3.00/0. 00 3.00/0.00 3.00/0.00 3.00/0.00 ns, min t spiccm mosi clock to out 8.00 8 .00 8.00 8.00 9.00 ns, max t spiccfc fcs_b clock to out 8.00 8 .00 8.00 8.00 9.00 ns, max startupe2 ports t usrcclko startupe2 usrcclko input to cclk output 0.50/6 .00 0.50/6.70 0.50/7.50 0 .50/7.50 0. 50/7.50 ns, min/max f cfgmclk startupe2 cfgmclk output frequency 6 5.00 65.00 65.00 65.00 65.00 mhz, typ f cfgmclktol startupe2 cfgmclk output frequency tolerance 50 50 50 50 50 %, max table 66: configuration switching characteristics (cont?d) symbol description speed grade units 1.0v 0.95v 0.9v -3 -2/-2le -1 -1li -2le s e n d f e e d b a c k
artix-7 fpgas data sheet: dc and ac switching characteristics ds181 (v1.21) september 27, 2016 www.xilinx.com product specification 59 efuse programming conditions table 67 lists the programming conditions specifically for efuse. for more information, see 7 series fpga configuration user guide ( ug470 ). revision history the following table shows the revi sion history for this document: device dna access port f dnack dna access port (dna_port) 100.00 100.00 100.00 100.00 70.00 mhz, max notes: 1. to support longer delays in configuration, use the design solutions described in 7 series fpga configuration user guide ( ug470 ). 2. only during configuration, the last edge is determi ned by a weak pull-up/pull-down resistor in the i/o. table 67: efuse programming conditions (1) symbol description min typ max units i fs v ccaux supply current ? ? 115 ma t j temperature range 15 ? 125 c notes: 1. the fpga must not be configured during efuse programming. date version description 09/26/2011 1.0 initial xilinx release. 11/07/2011 1.1 revised the v ocm specification in table 11 . updated the ac switching characteristics based upon the ise 13.3 software v1.02 speed specific ation throughout document including table 13 and table 14 . added mmcm_t fbdelay while adding mmcm_ to the symbol names of a few specifications in table 37 and pll to the symbol names in table 38 . in table 39 through table 46 , updated the pin-to- pin description with the sstl15 st andard. updated units in table 46. 02/13/2012 1.2 updated the artix-7 fam ily of devices listed throughout the entire data sheet. updated the ac switching characteristics based upon the ise 13.4 software v1.03 for the -3, -2, and -1 speed grades and v1.00 for the -2l speed grade. updated summary description on page 1 . in table 2 , revised v cco for the 3.3v hr i/o banks and updated t j . updated the notes in table 5 . added mgtavcc a nd mgtavtt power supply ramp times to table 7 . rearranged table 8 , added mobile_ddr, hstl_i_18 , hstl_ii_18, hsul_12, sstl135_r, sstl15_r, and sstl12 and re moved diff_sstl135, diff_sstl18_i, diff_sstl18_ii, diff_hstl_ i, and diff_hstl_ii. added table 9 and table 10 . revised the specifications in table 11 . revised v in in table 50 . updated the efuse programming conditions section and removed the endurance ta ble. added the table. revised f txin and f rxin in table 56 . revised i ccadc and updated note 1 in table 65 . revised ddr lvds trans mitter data width in table 15 . removed notes from table 27 as they are no longer applicable. updated specifications in table 66 . updated note 1 in table 36 . table 66: configuration switching characteristics (cont?d) symbol description speed grade units 1.0v 0.95v 0.9v -3 -2/-2le -1 -1li -2le s e n d f e e d b a c k
artix-7 fpgas data sheet: dc and ac switching characteristics ds181 (v1.21) september 27, 2016 www.xilinx.com product specification 60 06/01/2012 1.3 reorganized entire data sheet including adding table 43 and table 47 . updated t sol in table 1 . updated i batt and added r in_term to table 3 . updated power-on/off power supply sequencing section with regards to gtp transceivers. in table 8 , updated many parameters including sstl135 and sstl135_r. removed v ox column and added diff_hsul_12 to table 10 . updated v ol in table 11 . updated table 15 and removed notes 2 and 3. updated table 16 . updated the ac switching characteristics based upon the ise 14.1 software v1.03 for the -3, -2, -2l (1.0v), -1, and v1.01 for the -2l (0.9v) spe ed specifications thro ughout the document. in table 30 , updated reset delays section including note 10 and note 11 . in table 56 , replaced f txout with f glk . updated many of the xadc specifications in table 65 and added note 2 . updated and moved dynamic reconfiguration port (drp) for mmcm before and after dclk section from table 66 to table 37 and table 38 . 09/20/2012 1.4 in table 1 , updated the descriptions, changed v in and note 2 , and added note 4 . in table 2 , changed descriptions and notes. updated parameters in table 3 . added table 4 . revised the power-on/off power supply sequencing section. updated standards and specifications in table 8 , table 9 , and table 10 . removed the xc7a350t device from data sheet. updated the ac switching characteristics section to the ise 14.2 speed specifications throughout the document. updated the iob pad input/output/3-state discussion and changed table 18 by adding t ioibufdisable . removed many of the combinator ial delay specifications and t cinck /t ckcin from table 27 .changed f pfdmax conditions in table 37 and table 38 . updated the gtp transceiver specifications section, moved the gtp transceiver dc characteristics section to the overall dc characteristics section, and added the gtp transceiver protocol jitter characteristics section. in table 65 , updated note 1 . in table 66 , updated t por . 02/01/2013 1.5 updated the ac switching characteristics based upon the 14.4/2012.4 device pack for ise 14.4 and vivado 2012.4, both at v1.07 for the -3, -2, -2l (1.0 v), -1 speed specificatio ns, and v1.05 for the -2l (0.9v) speed specifications throughout the document. production changes to table 13 and table 14 for -3, -2, -2l (1.0v), -1 speed specifications. revised i dcin and i dcout and added note 5 in table 1 . added note 2 to table 2 . updated table 5 . added minimum current specifications to table 6 . removed sstl12 and hstl_i_12 from table 8 . removed diff_sstl12 from table 10 . updated table 13 . added a 2:1 memory controller section to table 16 . updated note 1 in table 34 . revised table 36 . updated note 1 and note 2 in table 49 . updated d vppin in table 50 . updated v idiff in table 51 . removed t lock and t phase and revised f gclk in table 54 . updated t dlock in table 55 . updated table 56 . in table 57 , updated t rtx , t ftx , v txoobvdpp , and revised note 1 through note 7 . in table 58 , updated rx sst and rx ppmtol and revised note 4 through note 7 . in table 63 , revised and added note 1 . revised the maximum external channel input ranges in table 65 . in table 66 , revised f mcck and added the internal configuration access port section. 04/17/2013 1.6 updated the ac switching characteristics based upon v1.07 of the ise 14.5 and vivado 2013.1 for the -3, -2, -2l (1.0v), and -1 speed specifications, and v1.05 for the -2l (0.9v) speed specifications. production changes to table 13 and table 14 for -2l (0.9v) speed specifications. in table 1 , revised v in (i/o input voltage) to match values in table 4 and combined note 4 with old note 5 and then added new note 5 . revised v in description, removed note 10, and added note 7 in table 2 . updated first 3 rows in table 4 . also revised pci33_3 voltage minimum in table 8 to match values in table 1 and table 4 . added note 1 to table 11 . removed note 1 from table 14 . updated table 16 title. throughout the data sheet ( table 28 , table 29 , and table 44 ) removed the obvious note ?a zero ?0? hold time listing indicates no hold time or a negative hold time.? 09/04/2013 1.7 added new artix-7 devices (xc7 a35t, xc7a50t, and xc7a75t) throughout. in table 1 , updated i dcin and i dcout for cases when floating, at v mgtavtt , or gnd. added back note 1 to table 14 . added cpg package to table 50 and table 52 . 11/27/2013 1.8 added automotive and ex panded temperature range artix-7 devices throughout. added -1m and -1q speed grades throughout. added reference to 7 series fpgas overview , defense-grade 7 series fpgas overview , and xa artix-7 fpgas overview in introduction . in table 2 , added junction temperature operating ranges for expanded (q) and mili tary (m) device s, and added note 3 . in table 3 , removed commercial (c), indu strial (i), and extended (e) from descriptions of r in_term . updated temperature ranges in table 4 . removed notes from table 6 . added t j = 125c to conditions column for t vcco2vccaux in table 7 . in ac switching characteristics , updated first paragraph, added table 12 , and added -1q/-1m speed grades to other tables in this section. in table 52 , added rb and rs packages, and updated f gtpmax . in table 65 , updated adc accuracy, on-chip sensors, xadc reference sections and notes. added t usrcclko and f dnack to table 66 . date version description s e n d f e e d b a c k
artix-7 fpgas data sheet: dc and ac switching characteristics ds181 (v1.21) september 27, 2016 www.xilinx.com product specification 61 01/07/2014 1.9 in table 13 , promoted all xc7a75t speed grades from advance to produc tion and all xq7a50t speed grades from preliminary to advance. in table 14 , inserted ?vivado tools 2013.3? for the production xc7a75t speed grades. 01/23/2014 1.10 updated the ac switching characteristics based upon ise 14.7 and vivado 2013.4. updated note 5 in table 2 . removed pad pull-down @ v in =1.8v for i rpd in table 3 . added note 2 to table 4 . removed xq7a50t from table 12 , table 13 , and table 14 . in table 13 , changed speed grades for xa artix-7 fpgas and defense-grade ar tix-7q family from -2 to -2i and -1 to -1i, and moved all speed grades of xa7a100t, and -1i and -2i speed grades of xq7a100t from preliminary to production. in table 14 , updated production software for xa7a100t and xq7a100t. added hsul_12_f, diff_hsul_12_f, mobile_ddr_s, mobile_ddr_f , diff_mobile_ddr_s, and diff_mobile_ddr_f to table 17 . removed introductory text in device pin-to-pin output parameter guidelines . 03/04/2014 1.11 updated note 2 in table 4 . in table 13 , moved xq7a100t -1m speed grade from preliminary to production. in table 14 , added production software for xq7a100t -1m speed grade. 03/28/2014 1.12 in table 5 , added i ccintq , i ccoq , i ccauxq , and i ccbramq values for xc7a35t, xc7a50t, xa7a35t, xa7a50t, and xq7a50t devices. in table 6 , added power-on current values for xc7a35t, xc7a50t, xa7a35t, xa7a50t, and xq7a50t devices. in table 12 , added row for xc7a35t, xc7a50t, and xc7a75t devices. in table 13 , moved all speed grades of xc7a35t and xc7a50t devices from advance to production, and added xq7a50t. in table 14 , added xq7a50t and production software for xc7a35t and xc7a50t -3, -2, -2l (1.0v), -1, and -2l (0.9v) speed grades. for f idelayctrl_ref in table 25 , updated refclk frequency of 300 mhz, added refclk frequency of 400 mhz, and updated note 1 . in table 36 , added t ckskew data for xc7a35t and xc7a50t devices. in table 39 , updated t ickof data for -1 and -2l (0.9v) speed grades of xc7a35t and xc7a50t devices. in table 40 , updated t ickoffar data for -1 and -2l (0.9v) speed grades of xc7a35t and xc7a50t devices. in table 41 , added t ickofmmcmcc data for -2l (0.9v) speed grade of xc7a35t and xc7a50t devices. in table 42 , added t ickofpllcc data for -2l (0.9v) speed grade of xc7a35t and xc7a50t devices. in table 44 , updated t psfd /t phfd data for -2/-2l, -1, and -2l (0.9v) speed grades of xc7a35t and xc7a50t devices. in table 45 , updated t psmmcmcc /t phmmcmcc data for -1 and -2l (0.9v) speed grades of xc7a35t and xc7a50t devices. in table 46 , updated t pspllcc /t phpllcc data for -1 and -2l (0.9v) speed gra des of xc7a35t and xc7a50t devices. in table 49 , added package skew values for xc7a35t, xc7a50t , xa7a35t, xa7a50t, and xq7a50t devices. 05/13/2014 1.13 in ac switching characteristics , updated to vivado 2014.1. in table 12 , updated vivado 2014.1 version numbers and consolidated rows. in table 13 , moved all xa7a75t speed grades from advance to preliminary and all xq7a200t speed grades from preliminary to production. in table 14 , added production software for xq7a200t -2, -1, and -1m speed grades. added timing data for xa7a35t, xa7a50t, xa7a75t, and xq7a50t devices to table 39 , table 40 , table 41 , table 42 , table 44 , table 45 , and table 46 . 07/01/2014 1.14 updated note 2 in table 4 per the customer notice xcn14014 : 7 series fpga and zynq-7000 ap soc i/o undershoot voltage data sheet update . in power-on/off power supply sequencing , added sentence about there being no recommended sequence for supplies not shown. in ac switching characteristics , updated to vivado 2014.2. in table 12 , added row for xq7a50t. in table 13 , moved all xq7a50t speed grades from advance to production. in table 14 , added production software for xq7a50t -2, -1, and -1m speed grades. in table 36 , added t ckskew values for xa7a35t, xa7a50t, and xq7a50t. updated description of t ickof in table 39 and added note 2 . updated description of t ickoffar in table 40 and added note 2 . in table 50 , moved dv ppout value of 1000 mv from max to min column, updated v in dc parameter description, and added note 2 . added ?peak-to-peak? to labels in figure 3 and figure 4 . added note after figure 4 . added note 1 to table 64 . in table 66 , replaced usrcclk output with startupe2 ports and added f cfgmclk and f cfgmclktol . 09/23/2014 1.15 removed 3.3v as descriptor of hr i/o banks throughout. updated note 3 in table 5 . in table 13 , moved all xa7a35t and xa7a50t speed grades from advance to production, and all xa7a75t speed grades from preliminar y to production. in table 14 , added production software for xa7a35t, xa7a50t, and xa7a75t -2, -1, and -1q speed grades, and removed note 2. added i/o standard adjustment measurement methodology . 10/09/2014 1.16 added xc7a15t and xa7a15t devices. added -1li speed grade throughout. updated introduction . added -1li (0.95v) to description of v ccint and v ccbram in table 2 . updated note 1 and added note 2 to table 14 . date version description s e n d f e e d b a c k
artix-7 fpgas data sheet: dc and ac switching characteristics ds181 (v1.21) september 27, 2016 www.xilinx.com product specification 62 notice of disclaimer the information disclosed to you hereunder (t he ?materials?) is provided solely for th e selection and use of xilinx products. t o the maximum extent permitted by applicable law: (1) materials are made available ?as is? and with all faults, xilinx hereby disclai ms all warranties and conditions, express, implied, or st atutory, including but not limited to warranties of merchantability, non-infringement, or fitness for any partic ular purpose; and (2) xilinx sh all not be liable (whether in contract or tort, including negligence, or und er any other theory of liability) for any loss or damage of any kind or nature re lated to, arising under, or in connection with, the materials (including your use of the materials), including for any direct, indirect, special, incidental, or consequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action brought by a third party) even if such damage or loss was reas onably foreseeable or xilinx had been advised of the possibility of the same. xilinx assumes no obligation to correct any e rrors contained in the materi als, or to advise you of any corrections or update. y ou may not reproduce, modify, distribute, or publicly display the materials without prior writte n consent. certain pr oducts are subject to the terms and conditions of xilinx?s limited warranty, please refer to xilinx?s terms of sale which can be viewed at www.xilinx.com/legal.htm#tos ; ip cores may be subject to warranty and su pport terms contained in a license issued to you by xilinx. xilinx products are not designed o r intended to be fail-safe or for use in any application requiring fail-safe performance; you assume sole risk and liability for use of xi linx products in such critical applications, please refer to xilinx?s terms of sale which can be viewed at www.xilinx.com/legal.htm#tos . automotive applications disclaimer automotive products (identified as ?xa? in the part number) are not warranted for use in the deployment of airbags or for use in applications that affect control of a vehicl e (?safety application?) unless there is a safety concept or redundancy feature consistent with the iso 26262 automoti ve safety standard (?safety design?). customer shall, prior to using or distributing any systems that incorporate products, thoroughly test such systems for safety purposes. use of products in a safety application without a safety design is fully at the risk of customer, subject only to applicable laws and regulations governing limitations on product liability. 11/19/2014 1.17 replaced -2l speed grade with - 2le throughout. updated descriptions of v ccint and v ccbram in table 2 . updated the ac switching characteristics based upon vivado 2014.4. in table 12 , updated vivado software version and added a row for v ccint = 0.95v. in table 13 , moved all speed grades for all devices from advance to production. in table 14 , added vivado 2014.4 software version to -1li (0.95v) speed grade column for commercial devices and applicable speed grades for xc7a15t and xa7a15t devices, and removed table notes . added selecting the correct speed grade and voltage in the vivado tools . in table 16 , moved lpddr2 row to end of 2: 1 memory controllers section. updated speed grade heading row in table 52 . 03/18/2015 1.18 in table 11 , changed maximum v icm value from 1.425v to 1.500v. removed lvds 1.8v standard from table 19 and table 20 . removed minimum sample rate specification from table 65 . 09/24/2015 1.19 updated first paragraph in introduction . assigned quiescent supply currents to -1li speed grade artix-7q devices in table 5 . in table 14 , changed -1li speed grade artix-7q device cells from n/a to blank and added note 1 . removed diff_sstl12 standard from table 19 and table 20 . changed -1li speed grade artix-7q device cells from n/a to blank in table 36 , table 39 , table 40 , table 41 , table 42 , table 44 , table 45 , and table 46 . added sbv484, fbv484, fbv676, and ffv1156 packages to table 49 . removed pb-free g suffix from packages in table 50 and table 52 . 11/24/2015 1.20 in ac switching characteristics , updated to vivado 2015.4. in table 13 , added -1li (0.95v) speed grade to production column for xq 7a50t, xq7a100t, and xq7a200t. in table 14 , removed table note and added vivado 2015.4 software version to -1 li (0.95v) speed grade column for xq7a50t, xq7a100t, and xq7a200t. in table 36 , added t ckskew for xq7a50t, xq7a100t, and xq7a200t at -1li (0.95v) speed grade. updated devi ce pin-to-pin output parameter tables ( table 39 to table 42 ) and input parameter tables ( table 44 to table 46 ) for xq7a50t, xq7a100t, and xq7a200t at -1li (0.95v) speed grade. 09/27/2016 1.21 added xc7a12t and xc7a25t devices. updated the ac switching characteristics based upon vivado 2016.3. in table 19 , updated v meas values for lvcmos 3.3v, lvttl 3.3v, and pci33 3.3v, and removed note 1. removed lv dci_15, hslvdci_15, lvdci_15, and hslvdci_18 i/o standards from table 20 . date version description s e n d f e e d b a c k

▲Up To Search▲

Price & Availability of LVCMOS12-F12

	To Download LVCMOS12-F12 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .